[PATCH] drm/radeon: Disable writeback by default on ppc

[Benjamin Herrenschmidt]

On Mon, 2013-06-17 at 18:57 -0400, Alex Deucher wrote:

> Weird.  I wonder if there is an issue with cache snoops on PPC.  We
> currently use the gart in cached mode (GPU snoops CPU cache) with
> cached pages.  I wonder if we need to use uncached pages on PPC.

There is no such issue and no known bugs with DMA writes on those
PCIe host bridges (and they do get hammered pretty bad here).

This needs further investigation by the lab/hw guys to find out what's
actually happening on the bus and the host bridge.

Thadeu, Kleber: Jerome suggested writing a test case in userspace that
continuously writes to a spare scratch register (thus triggering the
corresponding writeback DMA) and checks the memory location to compare
the writeback value (using a debugfs file for example, or mmap).

Can you guys do something like that ? Then we need the analyzer on
and/or the lab guys to look at the fabric trace & PHB trace.
 
Ben.