[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

Anssi Hannula anssi.hannula at iki.fi
Mon Nov 11 14:10:00 PST 2013


11.11.2013 17:55, Alex Deucher kirjoitti:
> On Fri, Nov 8, 2013 at 6:24 AM, Anssi Hannula <anssi.hannula at iki.fi> wrote:
>> 18.10.2013 23:41, Alex Deucher kirjoitti:
>>> Needed by the hda driver to properly set up synchronization
>>> on the audio side.
>>>
>>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>>> ---
>>>  drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
>>>  drivers/gpu/drm/radeon/evergreend.h     | 38 +++++++++++++++++++++++++++++++++
>>>  2 files changed, 75 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>>> index 5fbe486..abdc893 100644
>>> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
>>> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
>> [...]
>>> +             if (connector->latency_present[0])
>>> +                     tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
>>> +                             AUDIO_LIPSYNC(connector->audio_latency[0]);
>>> +             else
>>> +                     tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
>>> +     }
>>> +     WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
>> [...]
>>> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC         0x5fe8
>>> +#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)
>>> +#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)
>>> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
>>> + * 0   = invalid
>>> + * x   = legal delay value
>>> + * 255 = sync not supported
>>> + */
>>
>> Hmm, AMD_HDA_verbs_v2.pdf says that:
>> 0      = unknown latency
>>
>> HDMI spec 1.4 says that:
>> 0      = not valid or unknown latency
>> 1..251 = valid delay value
>> 255    = video not supported / audio not supported
>>
>> Are you sure you shouldn't use 0 instead for unknown (no latency_present)?
> 
> I'm not sure.  The comment in the code above is what the register spec
> says which seems to match the HDMI spec.  I can dig around a bit more
> internally.

OK, though don't waste too much time on that, ALSA has to handle 0 and
255 the same in any case (a patch has just been pushed to sound git to
handle 255). :)

-- 
Anssi Hannula



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