[PATCH v2 08/27] drm/tegra: gr2d: Miscellaneous cleanups

[Erik Faye-Lund]

On Tue, Oct 8, 2013 at 7:48 AM, Terje Bergström <tbergstrom at nvidia.com> wrote:
> On 07.10.2013 16:02, Erik Faye-Lund wrote:
>> So the question is really how the hardware treats writes to
>> non-existent registers. My guess would be that they are simply not
>> recorded, and if that's the case it doesn't matter what we do. And
>> doing an unconditional AND is faster than doing a bit-test followed by
>> a conditional branch.
>
> Hardware ignores writes to non-existent registers. Sometimes
> non-existent registers are taken into use in future versions, though.

Right. That might be a motivation to treat non-existent registers as
errors. But then I start to wonder about "holes" in the pointer
address space should be treated differently. For instance, from the
TRM it looks like registers 0x3 - 0x8, 0xe, 0x15 and 0x42 are
undefined for T20. If writes to registers beyond 0x4c fails, shouldn't
these also fail? Or are somehow guaranteed that these holes will never
be plugged? Are they simply missing from the TRM?

I dunno...