[PATCH 1/2] drm/radeon/audio: write audio/video latency info for DCE4/5

[Christian König]

Am 18.10.2013 22:41, schrieb Alex Deucher:
> Needed by the hda driver to properly set up synchronization
> on the audio side.
>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

For both: Reviewed-by: Christian König <christian.koenig at amd.com>

> ---
>   drivers/gpu/drm/radeon/evergreen_hdmi.c | 37 ++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/radeon/evergreend.h     | 38 +++++++++++++++++++++++++++++++++
>   2 files changed, 75 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/evergreen_hdmi.c b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> index 5fbe486..abdc893 100644
> --- a/drivers/gpu/drm/radeon/evergreen_hdmi.c
> +++ b/drivers/gpu/drm/radeon/evergreen_hdmi.c
> @@ -58,6 +58,42 @@ static void evergreen_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t cloc
>   	WREG32(HDMI_ACR_48_1 + offset, acr.n_48khz);
>   }
>   
> +static void dce4_afmt_write_latency_fields(struct drm_encoder *encoder,
> +					   struct drm_display_mode *mode)
> +{
> +	struct radeon_device *rdev = encoder->dev->dev_private;
> +	struct drm_connector *connector;
> +	struct radeon_connector *radeon_connector = NULL;
> +	u32 tmp = 0;
> +
> +	list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
> +		if (connector->encoder == encoder) {
> +			radeon_connector = to_radeon_connector(connector);
> +			break;
> +		}
> +	}
> +
> +	if (!radeon_connector) {
> +		DRM_ERROR("Couldn't find encoder's connector\n");
> +		return;
> +	}
> +
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		if (connector->latency_present[1])
> +			tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
> +				AUDIO_LIPSYNC(connector->audio_latency[1]);
> +		else
> +			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> +	} else {
> +		if (connector->latency_present[0])
> +			tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
> +				AUDIO_LIPSYNC(connector->audio_latency[0]);
> +		else
> +			tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
> +	}
> +	WREG32(AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC, tmp);
> +}
> +
>   static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
>   {
>   	struct radeon_device *rdev = encoder->dev->dev_private;
> @@ -327,6 +363,7 @@ void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode
>   		dce6_afmt_write_sad_regs(encoder);
>   	} else {
>   		evergreen_hdmi_write_sad_regs(encoder);
> +		dce4_afmt_write_latency_fields(encoder, mode);
>   	}
>   
>   	err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
> diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
> index fa81893..11e002a 100644
> --- a/drivers/gpu/drm/radeon/evergreend.h
> +++ b/drivers/gpu/drm/radeon/evergreend.h
> @@ -750,6 +750,44 @@
>    * bit6 = 192 kHz
>    */
>   
> +#define AZ_CHANNEL_COUNT_CONTROL                          0x5fe4
> +#       define HBR_CHANNEL_COUNT(x)                       (((x) & 0x7) << 0)
> +#       define COMPRESSED_CHANNEL_COUNT(x)                (((x) & 0x7) << 4)
> +/* HBR_CHANNEL_COUNT, COMPRESSED_CHANNEL_COUNT
> + * 0   = use stream header
> + * 1-7 = channel count - 1
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_LIPSYNC         0x5fe8
> +#       define VIDEO_LIPSYNC(x)                           (((x) & 0xff) << 0)
> +#       define AUDIO_LIPSYNC(x)                           (((x) & 0xff) << 8)
> +/* VIDEO_LIPSYNC, AUDIO_LIPSYNC
> + * 0   = invalid
> + * x   = legal delay value
> + * 255 = sync not supported
> + */
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_HBR             0x5fec
> +#       define HBR_CAPABLE                                (1 << 0) /* enabled by default */
> +
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION0 0x5ff4
> +#       define DISPLAY0_TYPE(x)                           (((x) & 0x3) << 0)
> +#       define DISPLAY_TYPE_NONE                   0
> +#       define DISPLAY_TYPE_HDMI                   1
> +#       define DISPLAY_TYPE_DP                     2
> +#       define DISPLAY0_ID(x)                             (((x) & 0x3f) << 2)
> +#       define DISPLAY1_TYPE(x)                           (((x) & 0x3) << 8)
> +#       define DISPLAY1_ID(x)                             (((x) & 0x3f) << 10)
> +#       define DISPLAY2_TYPE(x)                           (((x) & 0x3) << 16)
> +#       define DISPLAY2_ID(x)                             (((x) & 0x3f) << 18)
> +#       define DISPLAY3_TYPE(x)                           (((x) & 0x3) << 24)
> +#       define DISPLAY3_ID(x)                             (((x) & 0x3f) << 26)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_ASSOCIATION1 0x5ff8
> +#       define DISPLAY4_TYPE(x)                           (((x) & 0x3) << 0)
> +#       define DISPLAY4_ID(x)                             (((x) & 0x3f) << 2)
> +#       define DISPLAY5_TYPE(x)                           (((x) & 0x3) << 8)
> +#       define DISPLAY5_ID(x)                             (((x) & 0x3f) << 10)
> +#define AZ_F0_CODEC_PIN0_CONTROL_RESPONSE_AV_NUMBER       0x5ffc
> +#       define NUMBER_OF_DISPLAY_ID(x)                    (((x) & 0x7) << 0)
> +
>   #define AZ_HOT_PLUG_CONTROL                               0x5e78
>   #       define AZ_FORCE_CODEC_WAKE                        (1 << 0)
>   #       define PIN0_JACK_DETECTION_ENABLE                 (1 << 4)