[PATCH libdrm] radeon: Fix 1D tiling for CIK

[Christian König]

Am 18.09.2013 17:54, schrieb Alex Deucher:
> On Wed, Sep 18, 2013 at 9:51 AM, Michel Dänzer <michel at daenzer.net> wrote:
>> From: Michel Dänzer <michel.daenzer at amd.com>
>>
>> The main difference is that the tiling mode index changed for 1D tiled
>> depth/stencil surfaces.
>>
>> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
> One comment below, other than that,
>
> Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
>
>> ---
>>   include/drm/radeon_drm.h | 15 +++++++++++++++
>>   radeon/radeon_surface.c  | 15 ++++++++++++---
>>   2 files changed, 27 insertions(+), 3 deletions(-)
>>
>> diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
>> index 86cef15..533c3dc 100644
>> --- a/include/drm/radeon_drm.h
>> +++ b/include/drm/radeon_drm.h
>> @@ -1004,4 +1004,19 @@ struct drm_radeon_info {
>>   #define SI_TILE_MODE_DEPTH_STENCIL_2D_4AA      3
>>   #define SI_TILE_MODE_DEPTH_STENCIL_2D_8AA      2
>>
>> +#define CIK_TILE_MODE_COLOR_LINEAR_ALIGNED     8
>> +#define CIK_TILE_MODE_COLOR_1D                 13
>> +#define CIK_TILE_MODE_COLOR_1D_SCANOUT         9
>> +#define CIK_TILE_MODE_COLOR_2D_8BPP            14
>> +#define CIK_TILE_MODE_COLOR_2D_16BPP           15
>> +#define CIK_TILE_MODE_COLOR_2D_32BPP           16
>> +#define CIK_TILE_MODE_COLOR_2D_64BPP           17
>> +#define CIK_TILE_MODE_COLOR_2D_SCANOUT_16BPP   11
>> +#define CIK_TILE_MODE_COLOR_2D_SCANOUT_32BPP   12
>> +#define CIK_TILE_MODE_DEPTH_STENCIL_1D         5
>> +#define CIK_TILE_MODE_DEPTH_STENCIL_2D         0
And by the way, that looks a bit strange:
>> +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_2AA     3
>> +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_4AA     3


Christian.

>> +#define CIK_TILE_MODE_DEPTH_STENCIL_2D_8AA     2
>> +
> Can you send a patch to add these to radeon_drm.h in the kernel as well?
>
>>   #endif
>> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
>> index 818e26a..1710e34 100644
>> --- a/radeon/radeon_surface.c
>> +++ b/radeon/radeon_surface.c
>> @@ -1382,10 +1382,16 @@ static int si_surface_sanity(struct radeon_surface_manager *surf_man,
>>           break;
>>       case RADEON_SURF_MODE_1D:
>>           if (surf->flags & RADEON_SURF_SBUFFER) {
>> -            *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>> +            if (surf_man->family >= CHIP_BONAIRE)
>> +                *stencil_tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
>> +            else
>> +                *stencil_tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>>           }
>>           if (surf->flags & RADEON_SURF_ZBUFFER) {
>> -            *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>> +            if (surf_man->family >= CHIP_BONAIRE)
>> +                *tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
>> +            else
>> +                *tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>>           } else if (surf->flags & RADEON_SURF_SCANOUT) {
>>               *tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
>>           } else {
>> @@ -1643,7 +1649,10 @@ static int si_surface_init_2d(struct radeon_surface_manager *surf_man,
>>                   tile_mode = SI_TILE_MODE_COLOR_1D_SCANOUT;
>>                   break;
>>               case SI_TILE_MODE_DEPTH_STENCIL_2D:
>> -                tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>> +                if (surf_man->family >= CHIP_BONAIRE)
>> +                    tile_mode = CIK_TILE_MODE_DEPTH_STENCIL_1D;
>> +                else
>> +                    tile_mode = SI_TILE_MODE_DEPTH_STENCIL_1D;
>>                   break;
>>               default:
>>                   return -EINVAL;
>> --
>> 1.8.4.rc3
>>
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