PCI Radeon RV100 detection hang on sparc64
mroos at linux.ee
Wed Sep 25 16:26:09 PDT 2013
> > >> The pci_assign_resource() path must have some bug that causes the
> > >> resource values to be set incorrectly or similar.
> > >>
> > >> Meelis, what is the value of pci_resource_start(pdev, PCI_ROM_RESOURCE)
> > >> before the pci_map_rom() call?
> > >
> > > [drm] radeon_read_bios: pci_resource_start(ROM)=000001FF10020000
> > >
> > > I am a little confused here. ROM addressis OK but after pci_map_rom it
> > > results in address that corresponds to another device?
> > That's certainly a bug.
> > So after pci_map_rom() pci_resource_start(ROM)=000001FF00000000, right?
> I double checked it - yes:
> before pci_map_rom:
> [drm] radeon_read_bios: pci_resource_start(ROM)=000001FF10020000
> radeon 0000:02:02.0: BAR 6: assigned [mem 0x1ff00000000-0x1ff0001ffff]
> after pci_map_rom:
> [drm] radeon_read_bios, bios=000001ff00000000, pci_resource_start(ROM)=000001FF00000000, size=46592
This is first range in pci bus 0000:02 that is tried, and it matches:
pci_bus 0000:02: pci_bus_alloc_resource trying [mem 0x1ff00000000-0x1ff00bfffff]
I instrumented bootup with pci_bus_add_resource_offset and
pci_bus_add_resource logs if this of any help:
/pci at 1f,0: PCI IO[1fe02000000] MEM[1ff00000000]
/pci at 1f,0: SABRE PCI Bus Module ver[0:0]
PCI: Scanning PBM /pci at 1f,0
pci_bus_add_resource_offset adding [io 0x1fe02000000-0x1fe02ffffff]
pci_bus_add_resource_offset adding [mem 0x1ff00000000-0x1ffffffffff]
pci_bus_add_resource_offset adding [bus 00-02]
sabre f005f9c0: PCI host bridge to bus 0000:00
pci_bus 0000:00: pci_bus_add_resource adding [io 0x1fe02000000-0x1fe02ffffff] with flags 0
pci_bus 0000:00: root bus resource [io 0x1fe02000000-0x1fe02ffffff] (bus address [0x0000-0xffffff])
pci_bus 0000:00: pci_bus_add_resource adding [mem 0x1ff00000000-0x1ffffffffff] with flags 0
pci_bus 0000:00: root bus resource [mem 0x1ff00000000-0x1ffffffffff] (bus address [0x00000000-0xffffffff])
pci_bus 0000:00: root bus resource [bus 00-02]
To me it looks like we get the PCI bus ranges and store them and nobody
uses them until now, and then we insert PCI devices with allocations
from OF and do not update PCI bus available windows?
Meelis Roos (mroos at linux.ee)
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