[PATCH] drm/dp: constify DP DPCD helpers

[Alex Deucher]

On Fri, Sep 27, 2013 at 12:01 PM, Jani Nikula <jani.nikula at intel.com> wrote:
> None of the DP DPCD helpers need to modify the DPCD.
>
> Signed-off-by: Jani Nikula <jani.nikula at intel.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/drm_dp_helper.c |   16 ++++++++--------
>  include/drm/drm_dp_helper.h     |   16 ++++++++--------
>  2 files changed, 16 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/drm_dp_helper.c b/drivers/gpu/drm/drm_dp_helper.c
> index 89e1966..9e978aa 100644
> --- a/drivers/gpu/drm/drm_dp_helper.c
> +++ b/drivers/gpu/drm/drm_dp_helper.c
> @@ -228,12 +228,12 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter)
>  EXPORT_SYMBOL(i2c_dp_aux_add_bus);
>
>  /* Helpers for DP link training */
> -static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
> +static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
>  {
>         return link_status[r - DP_LANE0_1_STATUS];
>  }
>
> -static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
> +static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
>                              int lane)
>  {
>         int i = DP_LANE0_1_STATUS + (lane >> 1);
> @@ -242,7 +242,7 @@ static u8 dp_get_lane_status(u8 link_status[DP_LINK_STATUS_SIZE],
>         return (l >> s) & 0xf;
>  }
>
> -bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
> +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
>                           int lane_count)
>  {
>         u8 lane_align;
> @@ -262,7 +262,7 @@ bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_channel_eq_ok);
>
> -bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
> +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
>                               int lane_count)
>  {
>         int lane;
> @@ -277,7 +277,7 @@ bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
>
> -u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
> +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
>                                      int lane)
>  {
>         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
> @@ -290,7 +290,7 @@ u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
>
> -u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
> +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
>                                           int lane)
>  {
>         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
> @@ -303,7 +303,7 @@ u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
>  }
>  EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
>
> -void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
>         if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
>                 udelay(100);
>         else
> @@ -311,7 +311,7 @@ void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
>  }
>  EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
>
> -void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
> +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
>         if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
>                 udelay(400);
>         else
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index ae8dbfb..88661ad 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -333,20 +333,20 @@ i2c_dp_aux_add_bus(struct i2c_adapter *adapter);
>
>
>  #define DP_LINK_STATUS_SIZE       6
> -bool drm_dp_channel_eq_ok(u8 link_status[DP_LINK_STATUS_SIZE],
> +bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
>                           int lane_count);
> -bool drm_dp_clock_recovery_ok(u8 link_status[DP_LINK_STATUS_SIZE],
> +bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
>                               int lane_count);
> -u8 drm_dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
> +u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
>                                      int lane);
> -u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
> +u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
>                                           int lane);
>
>  #define DP_RECEIVER_CAP_SIZE           0xf
>  #define EDP_PSR_RECEIVER_CAP_SIZE      2
>
> -void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> -void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> +void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
> +void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]);
>
>  u8 drm_dp_link_rate_to_bw_code(int link_rate);
>  int drm_dp_bw_code_to_link_rate(u8 link_bw);
> @@ -379,13 +379,13 @@ struct edp_vsc_psr {
>  #define EDP_VSC_PSR_CRC_VALUES_VALID   (1<<2)
>
>  static inline int
> -drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +drm_dp_max_link_rate(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  {
>         return drm_dp_bw_code_to_link_rate(dpcd[DP_MAX_LINK_RATE]);
>  }
>
>  static inline u8
> -drm_dp_max_lane_count(u8 dpcd[DP_RECEIVER_CAP_SIZE])
> +drm_dp_max_lane_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
>  {
>         return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
>  }
> --
> 1.7.10.4
>
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