[PATCH] drm/radeon: fix audio pin counts for DCE6+
Alex Deucher
alexdeucher at gmail.com
Tue Apr 8 08:31:12 PDT 2014
On Tue, Apr 8, 2014 at 11:23 AM, Jerome Glisse <j.glisse at gmail.com> wrote:
> On Mon, Apr 07, 2014 at 04:17:21PM -0400, Alex Deucher wrote:
>> There is actually quite a bit of variance based on
>> the asic.
>>
>> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
>> Cc: stable at vger.kernel.org
>> ---
>> drivers/gpu/drm/radeon/dce6_afmt.c | 14 ++++++++++----
>> drivers/gpu/drm/radeon/radeon.h | 5 ++++-
>> 2 files changed, 14 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/radeon/dce6_afmt.c b/drivers/gpu/drm/radeon/dce6_afmt.c
>> index 8595449..38766aa 100644
>> --- a/drivers/gpu/drm/radeon/dce6_afmt.c
>> +++ b/drivers/gpu/drm/radeon/dce6_afmt.c
>> @@ -309,11 +309,17 @@ int dce6_audio_init(struct radeon_device *rdev)
>>
>> rdev->audio.enabled = true;
>>
>> - if (ASIC_IS_DCE8(rdev))
>> - rdev->audio.num_pins = 6;
>> - else if (ASIC_IS_DCE61(rdev))
>> + if (ASIC_IS_DCE81(rdev)) /* KV: 4 streams, 7 endpoints */
>> + rdev->audio.num_pins = 7;
>> + else if (ASIC_IS_DCE83(rdev)) /* KB: 2 streams, 3 endpoints */
>> rdev->audio.num_pins = 4;
>> - else
>
> This looks bogus, comment says 3 endpoint bit code set 4
Good catch. fixed up version sent out.
Thanks!
Alex
>
> Cheers,
> Jerome
>
>> + else if (ASIC_IS_DCE8(rdev)) /* BN/HW: 6 streams, 7 endpoints */
>> + rdev->audio.num_pins = 7;
>> + else if (ASIC_IS_DCE61(rdev)) /* TN: 4 streams, 6 endpoints */
>> + rdev->audio.num_pins = 6;
>> + else if (ASIC_IS_DCE64(rdev)) /* OL: 2 streams, 2 endpoints */
>> + rdev->audio.num_pins = 2;
>> + else /* SI: 6 streams, 6 endpoints */
>> rdev->audio.num_pins = 6;
>>
>> for (i = 0; i < rdev->audio.num_pins; i++) {
>> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
>> index 7a07ec8..f0fc2c8 100644
>> --- a/drivers/gpu/drm/radeon/radeon.h
>> +++ b/drivers/gpu/drm/radeon/radeon.h
>> @@ -736,7 +736,7 @@ union radeon_irq_stat_regs {
>> struct cik_irq_stat_regs cik;
>> };
>>
>> -#define RADEON_MAX_HPD_PINS 6
>> +#define RADEON_MAX_HPD_PINS 7
>> #define RADEON_MAX_CRTCS 6
>> #define RADEON_MAX_AFMT_BLOCKS 7
>>
>> @@ -2628,6 +2628,9 @@ void r100_pll_errata_after_index(struct radeon_device *rdev);
>> #define ASIC_IS_DCE64(rdev) ((rdev->family == CHIP_OLAND))
>> #define ASIC_IS_NODCE(rdev) ((rdev->family == CHIP_HAINAN))
>> #define ASIC_IS_DCE8(rdev) ((rdev->family >= CHIP_BONAIRE))
>> +#define ASIC_IS_DCE81(rdev) ((rdev->family == CHIP_KAVERI))
>> +#define ASIC_IS_DCE82(rdev) ((rdev->family == CHIP_BONAIRE))
>> +#define ASIC_IS_DCE83(rdev) ((rdev->family == CHIP_KABINI))
>>
>> #define ASIC_IS_LOMBOK(rdev) ((rdev->ddev->pdev->device == 0x6849) || \
>> (rdev->ddev->pdev->device == 0x6850) || \
>> --
>> 1.8.3.1
>>
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