[PATCH] drm/radeon: apply more strict limits for PLL params v2

[Alex Deucher]

On Fri, Apr 11, 2014 at 11:24 AM, Christian König
<deathsimple at vodafone.de> wrote:
> From: Christian König <christian.koenig at amd.com>
>
> Letting post and refernce divider get to big is bad for signal stability.
>
> v2: increase the limit to 210

Maybe mention the bug number?

>
> Signed-off-by: Christian König <christian.koenig at amd.com>

Reviewed-by: Alex Deucher <alexander.deucher at amd.com>

> ---
>  drivers/gpu/drm/radeon/radeon_display.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
> index 386cfa4..2f42912 100644
> --- a/drivers/gpu/drm/radeon/radeon_display.c
> +++ b/drivers/gpu/drm/radeon/radeon_display.c
> @@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
>         }
>         post_div = post_div_best;
>
> +       /* limit reference * post divider to a maximum */
> +       ref_div_max = min(210 / post_div, ref_div_max);
> +
>         /* get matching reference and feedback divider */
>         ref_div = max(den / post_div, 1u);
>         fb_div = nom;
> --
> 1.9.1
>
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