[PULL] first drm-intel-next for 3.18

Daniel Vetter daniel.vetter at ffwll.ch
Fri Aug 15 10:52:03 PDT 2014

Hi Dave,

So you made noises that you wanted to open drm-next right after -rc1, so
I've figured I'll test this ;-)

- Setting dp M2/N2 values plus state checker support (Vandana Kannan)
- chv power well support (Ville)
- DP training pattern 3 support for chv (Ville)
- cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien)
- dsi video burst mode support (Shobhit)
- piles of other chv fixes all over (Ville et. al.)
- cleanup of the ddi translation tables setup code (Damien)
- 180 deg rotation support (Ville & Sonika Jindal)

Cheers, Daniel

The following changes since commit a91576d7916f6cce76d30303e60e1ac47cf4a76d:

  drm/ttm: Pass GFP flags in order to avoid deadlock. (2014-08-05 10:54:19 +1000)

are available in the git repository at:

  git://anongit.freedesktop.org/drm-intel tags/drm-intel-next-2014-08-08

for you to fetch changes up to 2c0827cffca8ac0c654b888c58a1989a5172f007:

  drm/i915: Update DRIVER_DATE to 20140808 (2014-08-08 20:44:59 +0200)

- Setting dp M2/N2 values plus state checker support (Vandana Kannan)
- chv power well support (Ville)
- DP training pattern 3 support for chv (Ville)
- cleanup of the hsw/bdw ddi pll code, prep work for skl (Damien)
- dsi video burst mode support (Shobhit)
- piles of other chv fixes all over (Ville et. al.)
- cleanup of the ddi translation tables setup code (Damien)
- 180 deg rotation support (Ville & Sonika Jindal)

Damien Lespiau (15):
      drm/i915: Specify when the PLL hw state fields are valid
      drm/i915: Add a space to the shared DPLL debug message
      drm/i915: Extract the HSW DDI selection code into its own function
      drm/i915: Extract the HSW/BDW shared dpll init code
      drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDW
      drm/i915: Fix stale comment for intel_ddi_pll_select()
      drm/i915: Split the BDW/HSW specific shared pll selection
      drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specific
      drm/i915: Split the CDCLK retrieval per-platform
      drm/i915: Gather the HDMI level shifter logic into one place
      drm/i915/bdw: Provide the BDW specific HDMI buffer translation table
      drm/i915/bdw: Remove the HDMI/DVI entry from the DP/eDP/FDI tables
      drm/i915: Remove now useless comments about the translation values
      drm/i915: Demote the DRRS messages to debug messages
      drm/i915: Introduce a for_each_intel_encoder() macro

Daniel Vetter (8):
      drm/i915: Update DRIVER_DATE to 20140725
      drm/i915: Don't require dev->struct_mutex in psr_match_conditions
      drm/i915: Tune done rc6 enabling output
      drm/i915: Tune down MCH_SSKPD values warning
      drm/i915: Make ddi_clock_gate() HSW/BDW specific
      drm/i915: Align intel_dsi*.c files a bit
      drm/i915: No busy-loop wait_for in the ring init code
      drm/i915: Update DRIVER_DATE to 20140808

Deepak S (1):
      drm/i915: Bring GPU Freq to min while suspending.

Gajanan Bhat (4):
      drm/i915: Update DDL only for current CRTC
      drm/i915: Generalize drain latency computation
      drm/i915: Round-up clock and limit drain latency
      drm/i915: Add sprite watermark programming for VLV and CHV

Imre Deak (2):
      drm/i915: factor out intel_edp_panel_vdd_sanitize
      drm/i915: fix VDD state tracking after system resume

Jesse Barnes (1):
      drm/i915: clean up PPGTT checking logic

Jiri Kosina (1):
      drm/i915: read HEAD register back in init_ring_common() to enforce ordering

Kenneth Graunke (2):
      drm/i915: Refactor Broadwell PIPE_CONTROL emission into a helper.
      drm/i915: Add the WaCsStallBeforeStateCacheInvalidate:bdw workaround.

Mika Kuoppala (1):
      drm/i915: Don't accumulate hangcheck score on forward progress

Paulo Zanoni (2):
      d rm/i915: freeze display before the interrupts and GT
      drm/i915: remove duplicate register defines

Pavel Machek (1):
      drm/i915: work around warning in i915_gem_gtt

Rafael Barbalho (2):
      drm/i915: Fix crash when failing to parse MIPI VBT
      drm/i915: Fix read back of plane stride register

Rodrigo Vivi (5):
      drm/i915: Fix error state collecting
      drm/i915: Collect gtier properly on HSW.
      drm/i915: Fix DEIER and GTIER collecting for BDW.
      Revert "drm/i915: Enable semaphores on BDW"
      drm/i915: Introduce FBC False Color for debug purposes.

Shobhit Kumar (3):
      drm/i915: wait for all DSI FIFOs to be empty
      drm/i915: Add correct hw/sw config check for DSI encoder
      drm/i915: Add support for Video Burst Mode for MIPI DSI

Sonika Jindal (2):
      drm: Add rotation_property to mode_config
      drm: Resetting rotation property

Vandana Kannan (2):
      drm/i915: Set M2_N2 registers during mode set
      drm/i915: State readout and cross-checking for dp_m2_n2

Ville Syrjälä (27):
      drm/i915: Fix threshold for choosing 32 vs. 64 precisions for VLV DDL values
      drm: Add drm_crtc_vblank_waitqueue()
      drm/i915: Kill intel_crtc->vbl_wait
      drm/i915: Add chv_power_wells[]
      drm/i915: Add chv cmnlane power wells
      drm/i915: Kill intel_reset_dpio()
      drm/i915: Add disp2d power well for chv
      drm/i915: Add per-pipe power wells for chv
      drm/i915: Add chv port B and C TX wells
      drm/i915: Add chv port D TX wells
      drm/i915: Split a few long debug prints
      drm/i915: Add DP training pattern 3 for CHV
      drm/i915: Add cdclk change support for chv
      drm/i915: Disable cdclk changes for chv until Punit is ready
      drm/i915: Leave DPLL ref clocks on
      drm/i915: Split chv_update_pll() apart
      drm/i915: Call intel_{dp, hdmi}_prepare for chv
      drm/i915: Clarify CHV swing margin/deemph bits
      drm/i915: Add 180 degree sprite rotation support
      drm/i915: Make intel_plane_restore() return an error
      drm/i915: Add rotation property for sprites
      drm/i915: Fill out the FWx watermark register defines
      drm/i915: Parametrize VLV_DDL registers
      drm/i915: Add cherryview_update_wm()
      drm/i915: Hack to tie both common lanes together on chv
      drm/i915: Polish the chv cmnlane resrt macros
      drm/i915: Free pending page flip events at .preclose()

Zhenyu Wang (1):
      drm/i915: Fix drain latency precision multipler for VLV

 Documentation/DocBook/drm.tmpl             |   1 +
 drivers/gpu/drm/drm_fb_helper.c            |   9 +-
 drivers/gpu/drm/i915/i915_debugfs.c        |  45 ++-
 drivers/gpu/drm/i915/i915_dma.c            |   3 +
 drivers/gpu/drm/i915/i915_drv.c            |   4 +
 drivers/gpu/drm/i915/i915_drv.h            |  23 +-
 drivers/gpu/drm/i915/i915_gem.c            |   2 +-
 drivers/gpu/drm/i915/i915_gem_gtt.c        |  22 +-
 drivers/gpu/drm/i915/i915_gem_gtt.h        |   1 -
 drivers/gpu/drm/i915/i915_gpu_error.c      |  35 +-
 drivers/gpu/drm/i915/i915_irq.c            |  30 +-
 drivers/gpu/drm/i915/i915_reg.h            | 236 +++++++++----
 drivers/gpu/drm/i915/intel_bios.c          |  15 +-
 drivers/gpu/drm/i915/intel_bios.h          |   3 +-
 drivers/gpu/drm/i915/intel_ddi.c           | 171 ++++++---
 drivers/gpu/drm/i915/intel_display.c       | 344 ++++++++++++------
 drivers/gpu/drm/i915/intel_dp.c            | 117 +++---
 drivers/gpu/drm/i915/intel_drv.h           |  10 +-
 drivers/gpu/drm/i915/intel_dsi.c           |  67 +++-
 drivers/gpu/drm/i915/intel_dsi.h           |   3 +
 drivers/gpu/drm/i915/intel_dsi_cmd.c       |  16 +
 drivers/gpu/drm/i915/intel_dsi_cmd.h       |   1 +
 drivers/gpu/drm/i915/intel_dsi_panel_vbt.c |  38 +-
 drivers/gpu/drm/i915/intel_dsi_pll.c       |  94 ++++-
 drivers/gpu/drm/i915/intel_hdmi.c          |   8 +-
 drivers/gpu/drm/i915/intel_lvds.c          |   3 +-
 drivers/gpu/drm/i915/intel_pm.c            | 549 +++++++++++++++++++++++++----
 drivers/gpu/drm/i915/intel_ringbuffer.c    |  51 ++-
 drivers/gpu/drm/i915/intel_ringbuffer.h    |   2 +
 drivers/gpu/drm/i915/intel_sprite.c        |  98 ++++-
 include/drm/drmP.h                         |  11 +
 include/drm/drm_crtc.h                     |   1 +
 32 files changed, 1552 insertions(+), 461 deletions(-)

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

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