[PATCH] drm/radeon: save/restore the PD addr on suspend/resume

[Michel Dänzer]

On 26.08.2014 21:45, Christian König wrote:
> From: Christian König <christian.koenig at amd.com>
>
> This fixes a problem with GPU resets and TLB flushes on SI/CIK.
>
> Signed-off-by: Christian König <christian.koenig at amd.com>

[...]

> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index f2dba50..8810df3 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -918,6 +918,8 @@ struct radeon_vm_manager {
>   	u64				vram_base_offset;
>   	/* is vm enabled? */
>   	bool				enabled;
> +	/* for hw to save the PD addr on suspend/resume */
> +	uint32_t			saved_table_addr[RADEON_NUM_VM];
>   };
>
>   /*
> diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
> index 011779b..28b5f06 100644
> --- a/drivers/gpu/drm/radeon/si.c
> +++ b/drivers/gpu/drm/radeon/si.c
> @@ -4291,10 +4291,10 @@ static int si_pcie_gart_enable(struct radeon_device *rdev)
>   	for (i = 1; i < 16; i++) {
>   		if (i < 8)
>   			WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
> -			       rdev->gart.table_addr >> 12);
> +			       rdev->vm_manager.saved_table_addr[i]);
>   		else
>   			WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
> -			       rdev->gart.table_addr >> 12);
> +			       rdev->vm_manager.saved_table_addr[i]);
>   	}
>
>   	/* enable context1-15 */

rdev->vm_manager.saved_table_addr[] doesn't get initialized before 
*_gart_enable() is first called from *_startup(), does it? I guess 
that's fine, but the comments in *_gart_enable() should be adapted to 
this change.


-- 
Earthling Michel Dänzer            |                  http://www.amd.com
Libre software enthusiast          |                Mesa and X developer