[RFC] drm/ttm: dma: Fixes for 32-bit and 64-bit ARM

[Konrad Rzeszutek Wilk]

On Wed, Nov 12, 2014 at 06:03:49PM +0100, Arnd Bergmann wrote:
> On Wednesday 12 November 2014 09:18:59 Konrad Rzeszutek Wilk wrote:
> > On Wed, Nov 12, 2014 at 01:39:05PM +0100, Thierry Reding wrote:
> > > From: Thierry Reding <treding at nvidia.com>
> > > 
> > > dma_alloc_coherent() returns a kernel virtual address that is part of
> > > the linear range. Passing such an address to virt_to_page() is illegal
> > > on non-coherent architectures. This causes the kernel to oops on 64-bit
> > > ARM because the struct page * obtained from virt_to_page() points to
> > > unmapped memory.
> > 
> > Oh! That is not good!
> >
> I think what Thierry meant is that the returned pointer is /not/ in the
> linear range.
>  
> > > Until that time, this temporary fix will allow TTM to work on 32-bit
> > > and 64-bit ARM as well, provided that no IOMMU translations are enabled
> > > for the GPU.
> > 
> > Is there a way to query the 'struct device' to see if the IOMMU translation
> > is enabled/disabled for said device?

?
> > 
> > Now your patch looks to get the 'struct page' by doing some  form of
> > translation. Could you explain to me which type of memory have a 'struct page'
> > and which ones do not ?
> > 
> > It is OK if you explain this in nauseating details 
> 
> Basically there are two types of memory that have a struct page:
> 
> - directly mapped cacheable memory, i.e. anything that can be accessed
>   through a kernel pointer without having to go though ioremap/vmalloc/...
> 
> - highmem pages on 32-bit system.
> 
> On noncoherent ARM systems, dma_alloc_coherent will return memory that
> is was unmapped from the linear range to avoid having both cacheable and
> noncachable mappings for the same page.
> 
> 	Arnd