[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

Öyvind Saether <oyvinds at everdot.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |oyvinds at everdot.org

--- Comment #13 from Öyvind Saether <oyvinds at everdot.org> ---
Created attachment 111366
  --> https://bugs.freedesktop.org/attachment.cgi?id=111366&action=edit
dmesg 3.18.1 with drm debug=0x06

[    6.976062] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD
clocks!
[    6.976064] [drm:uvd_v1_0_ib_test] *ERROR* radeon: failed to raise UVD
clocks (-110).
[    6.976066] [drm:radeon_ib_ring_tests] *ERROR* radeon: failed testing IB on
ring 5 (-110).

on 3.18.1, could this be because the card is factory overclocked?

[    5.613512] [drm:radeon_pm_print_states] 4 Power State(s)
[    5.613512] [drm:radeon_pm_print_states] State 0: 
[    5.613513] [drm:radeon_pm_print_states]     Default
[    5.613514] [drm:radeon_pm_print_states]     16 PCIE Lanes
[    5.613514] [drm:radeon_pm_print_states]     1 Clock Mode(s)
[    5.613515] [drm:radeon_pm_print_states]             0 e: 860000     m:
1200000      v: 1210
[    5.613516] [drm:radeon_pm_print_states] State 1: Performance
[    5.613517] [drm:radeon_pm_print_states]     16 PCIE Lanes
[    5.613517] [drm:radeon_pm_print_states]     3 Clock Mode(s)
[    5.613518] [drm:radeon_pm_print_states]             0 e: 300000     m:
500000       v: 825
[    5.613519] [drm:radeon_pm_print_states]             1 e: 450000     m:
1225000      v: 900
[    5.613520] [drm:radeon_pm_print_states]             2 e: 1000000    m:
1225000      v: 1210
[    5.613520] [drm:radeon_pm_print_states] State 2: 
[    5.613521] [drm:radeon_pm_print_states]     16 PCIE Lanes
[    5.613521] [drm:radeon_pm_print_states]     3 Clock Mode(s)
[    5.613522] [drm:radeon_pm_print_states]             0 e: 450000     m:
1225000      v: 900
[    5.613522] [drm:radeon_pm_print_states]             1 e: 450000     m:
1225000      v: 900
[    5.613523] [drm:radeon_pm_print_states]             2 e: 1000000    m:
1225000      v: 1210
[    5.613524] [drm:radeon_pm_print_states] State 3: 
[    5.613524] [drm:radeon_pm_print_states]     1 PCIE Lanes
[    5.613525] [drm:radeon_pm_print_states]     3 Clock Mode(s)
[    5.613526] [drm:radeon_pm_print_states]             0 e: 300000     m:
500000       v: 825
[    5.613526] [drm:radeon_pm_print_states]             1 e: 300000     m:
500000       v: 825
[    5.613527] [drm:radeon_pm_print_states]             2 e: 300000     m:
500000       v: 825
[    5.613557] [drm] radeon: power management initialized

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