3.14-rc1 ring/display regression in "low" power_profile (drm/radeon/pm: move pm handling into the asic specific code)

[Rafał Miłecki]

01:00.0 VGA compatible controller [0300]: Advanced Micro Devices, Inc.
[AMD/ATI] Blackcomb [Radeon HD 6970M/6990M] [1002:6720]

I don't use dpm, but a profile method. Right after booting (without
touching power_profile) I can suspend & resume as many times as I want
(tested with ~50 s&r routines).

Starting with:
commit 6c7bccea390853bdec5b76fe31fc50f3b36f75d5
Author: Alex Deucher <alexander.deucher at amd.com>
Date: Wed Dec 18 14:07:14 2013 -0500

    drm/radeon/pm: move pm handling into the asic specific code

    We need more control over the ordering of dpm init with
    respect to the rest of the asic. Specifically, the SMC
    has to be initialized before the rlc and cg/pg. The pm
    code currently initializes late in the driver, but we need
    it to happen much earlier so move pm handling into the asic
    specific callbacks.

    This makes dpm more reliable and makes clockgating work
    properly on CIK parts and should help on SI parts as well.

    Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

I can't successfully resume using "low" power_profile. My testing
looks like this:
boot
s & r (result: GOOD)
s & r (result: GOOD)
s & r (result: GOOD)
echo "low" > /sys/class/drm/card0/device/power_profile
s & r (result: BAD)

BAD means display corruption [0] and:
[ 80.244475] [drm:r600_ring_test] *ERROR* radeon: ring 0 test failed
(scratch(0x8504)=0xCAFEDEAD)
[ 80.244475] [drm:evergreen_resume] *ERROR* evergreen startup failed on resume

[0] http://files.zajec.net/barts-low-resume-corruption.jpeg

-- 
Rafał
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