[PATCH V4 00/10] drm: exynos: few patches to enhance bridge chip support

Andreas Färber afaerber at suse.de
Wed Jul 2 22:19:18 PDT 2014


Hi Ajay,

Thanks a lot for your work on this.

Am 11.06.2014 20:26, schrieb Ajay Kumar:
> This series is based on exynos-drm-next branch of Inki Dae's tree at:
> git://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git
> 
> I have tested this after adding few DT changes for exynos5250-snow,
> exynos5420-peach-pit and exynos5800-peach-pi boards.

Unfortunately this series per se does not yet fix my display issues on
the Spring Chromebook. Can you share what dt changes you made for Snow?

Before, if the dp-controller dt node was present, I would get a dark
screen immediately and I could ssh into the system shortly after.
I worked around that by commenting the node out, which would allow me to
graphically boot pretty much instantly.

With these 10 patches applied on top of my dt on top of kgene's tree,
the last U-Boot screen stays visible for ~50 seconds, then the screen
goes blank, and I can ssh in some time later.
If I comment out the dp-controller node again, it takes long for the
kernel boot to graphically proceed but works okay then.
In both cases there's a gap of ~2900 seconds visible in dmesg.

Is presence of a framebuffer dt node or U-Boot not disabling FIMD
interfering here, i.e. do I need to replace nv U-Boot? Or do I need to
cherry-pick any preparatory patches from exynos-drm-next?

I'm building with LPAE, but the only two warnings in drm code I see are
about a NULL cast to dma_addr_t and a %x in debug code, which I consider
non-critical (but would be nice if Inki could silence them).

Regards,
Andreas

https://github.com/afaerber/linux/commits/spring-next
https://github.com/afaerber/u-boot/commits/spring

w/ dp-controller:

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.16.0-rc2+ (andreas at chrome11.site) (gcc
version 4.
8.2 20140404 [gcc-4_8-branch revision 209122] (SUSE Linux) ) #8 SMP
PREEMPT Thu
Jul 3 05:56:13 CEST 2014
[    0.000000] CPU: ARMv7 Processor [410fc0f4] revision 4 (ARMv7),
cr=30c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction
cache
[    0.000000] Machine model: Google Spring
[    0.000000] Forcing write-allocate cache policy for SMP
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] On node 0 totalpages: 523264
[    0.000000] free_area_init_node: node 0, pgdat c0659dc0, node_mem_map
ee7fc00
0
[    0.000000]   Normal zone: 1520 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 194560 pages, LIFO batch:31
[    0.000000]   HighMem zone: 2568 pages used for memmap
[    0.000000]   HighMem zone: 328704 pages, LIFO batch:31
[    0.000000] PERCPU: Embedded 7 pages/cpu @ee7bb000 s7104 r8192 d13376
u32768
[    0.000000] pcpu-alloc: s7104 r8192 d13376 u32768 alloc=8*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pag
es: 521744
[    0.000000] Kernel command line: console=tty1 root=/dev/sda3
rootfstype=ext4
rw rootwait clk_ignore_unused
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288
bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144
bytes)
[    0.000000] Memory: 2068780K/2093056K available (4454K kernel code,
258K rwdata, 1480K rodata, 278K init, 281K bss, 24276K reserved,
1314816K highmem)
[    0.000000] Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xffe00000   (2048 kB)
    vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc05d3dd4   (5936 kB)
      .init : 0xc05d4000 - 0xc0619bc0   ( 279 kB)
      .data : 0xc061a000 - 0xc065a9e0   ( 259 kB)
       .bss : 0xc065a9ec - 0xc06a1080   ( 282 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C: failed to init: -19
[    0.000000] Exynos5250: clock setup completed, armclk=1700000000
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (virt).
[    0.000002] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps
every 2863311519744ns
[    0.000007] Switching to timer-based delay loop
[ 2869.295699] sched_clock: 64 bits at 24MHz, resolution 41ns, wraps
every 2863311519744ns
[ 2869.295841] Console: colour dummy device 80x30
[ 2869.296042] console [tty1] enabled
[ 2869.296056] Calibrating delay loop (skipped), value calculated using
timer frequency.. 48.00 BogoMIPS (lpj=120000)
[ 2869.296073] pid_max: default: 32768 minimum: 301
[ 2869.296160] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 2869.296171] Mountpoint-cache hash table entries: 2048 (order: 1, 8192
bytes)
[ 2869.296520] CPU: Testing write buffer coherency: ok
[ 2869.296649] CPU0: update cpu_capacity 1024
[ 2869.296660] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 2869.296757] Setting up static identity map for 0x4043c0d8 - 0x4043c130
[ 2920.607940] CPU1: Booted secondary processor
[ 2920.607972] CPU1: update cpu_capacity 1024
[ 2920.607976] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 2920.608020] Brought up 2 CPUs
[...]

w/o dp-controller:

[    0.000000] Booting Linux on physical CPU 0x0
[    0.000000] Linux version 3.16.0-rc2+ (andreas at chrome11.site) (gcc
version 4.8.2 20140404 [gcc-4_8-branch revision 209122] (SUSE Linux) )
#8 SMP PREEMPT Thu Jul 3 05:56:13 CEST 2014
[    0.000000] CPU: ARMv7 Processor [410fc0f4] revision 4 (ARMv7),
cr=30c5387d
[    0.000000] CPU: PIPT / VIPT nonaliasing data cache, PIPT instruction
cache
[    0.000000] Machine model: Google Spring
[    0.000000] Forcing write-allocate cache policy for SMP
[    0.000000] Memory policy: Data cache writealloc
[    0.000000] On node 0 totalpages: 523264
[    0.000000] free_area_init_node: node 0, pgdat c0659dc0, node_mem_map
ee7fc000
[    0.000000]   Normal zone: 1520 pages used for memmap
[    0.000000]   Normal zone: 0 pages reserved
[    0.000000]   Normal zone: 194560 pages, LIFO batch:31
[    0.000000]   HighMem zone: 2568 pages used for memmap
[    0.000000]   HighMem zone: 328704 pages, LIFO batch:31
[    0.000000] PERCPU: Embedded 7 pages/cpu @ee7bc000 s7104 r8192 d13376
u32768
[    0.000000] pcpu-alloc: s7104 r8192 d13376 u32768 alloc=8*4096
[    0.000000] pcpu-alloc: [0] 0 [0] 1
[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.
Total pages: 521744
[    0.000000] Kernel command line: console=tty1 root=/dev/sda3
rootfstype=ext4 rw rootwait clk_ignore_unused
[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288
bytes)
[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144
bytes)
[    0.000000] Memory: 2068784K/2093056K available (4454K kernel code,
258K rwdata, 1480K rodata, 278K init, 281K bss, 24272K reserved,
1314816K highmem)
[    0.000000] Virtual kernel memory layout:
    vector  : 0xffff0000 - 0xffff1000   (   4 kB)
    fixmap  : 0xffc00000 - 0xffe00000   (2048 kB)
    vmalloc : 0xf0000000 - 0xff000000   ( 240 MB)
    lowmem  : 0xc0000000 - 0xef800000   ( 760 MB)
    pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)
    modules : 0xbf000000 - 0xbfe00000   (  14 MB)
      .text : 0xc0008000 - 0xc05d3dd4   (5936 kB)
      .init : 0xc05d4000 - 0xc0619bc0   ( 279 kB)
      .data : 0xc061a000 - 0xc065a9e0   ( 259 kB)
       .bss : 0xc065a9ec - 0xc06a1080   ( 282 kB)
[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1
[    0.000000] Preemptible hierarchical RCU implementation.
[    0.000000]  RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=2.
[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=2
[    0.000000] NR_IRQS:16 nr_irqs:16 16
[    0.000000] L2C: failed to init: -19
[    0.000000] Exynos5250: clock setup completed, armclk=1700000000
[    0.000000] Architected cp15 timer(s) running at 24.00MHz (virt).
[    0.000003] sched_clock: 56 bits at 24MHz, resolution 41ns, wraps
every 2863311519744ns
[    0.000007] Switching to timer-based delay loop
[ 2870.975122] sched_clock: 64 bits at 24MHz, resolution 41ns, wraps
every 2863311519744ns
[ 2870.975267] Console: colour dummy device 80x30
[ 2870.975468] console [tty1] enabled
[ 2870.975482] Calibrating delay loop (skipped), value calculated using
timer frequency.. 48.00 BogoMIPS (lpj=120000)
[ 2870.975499] pid_max: default: 32768 minimum: 301
[ 2870.975587] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
[ 2870.975598] Mountpoint-cache hash table entries: 2048 (order: 1, 8192
bytes)
[ 2870.975950] CPU: Testing write buffer coherency: ok
[ 2870.976081] CPU0: update cpu_capacity 1024
[ 2870.976092] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000
[ 2870.976188] Setting up static identity map for 0x4043c0d8 - 0x4043c130
[ 2920.607946] CPU1: Booted secondary processor
[ 2920.607979] CPU1: update cpu_capacity 1024
[ 2920.607983] CPU1: thread -1, cpu 1, socket 0, mpidr 80000001
[ 2920.608027] Brought up 2 CPUs
[...]

-- 
SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg


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