[PATCH 1/2] drm/radeon: s/ioctl_wait_idle/mmio_hpd_flush/
Alex Deucher
alexdeucher at gmail.com
Thu Jul 31 11:39:10 PDT 2014
On Thu, Jul 31, 2014 at 5:43 AM, Michel Dänzer <michel at daenzer.net> wrote:
> From: Michel Dänzer <michel.daenzer at amd.com>
>
> And clean up the function comment a little.
>
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
Applied the series to my 3.17 tree.
Alex
> ---
> drivers/gpu/drm/radeon/r600.c | 13 +++++------
> drivers/gpu/drm/radeon/radeon.h | 9 ++------
> drivers/gpu/drm/radeon/radeon_asic.c | 44 ++++++++++++++++++------------------
> drivers/gpu/drm/radeon/radeon_asic.h | 2 +-
> drivers/gpu/drm/radeon/radeon_gem.c | 6 ++---
> 5 files changed, 34 insertions(+), 40 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
> index c17ff5d..76e1616 100644
> --- a/drivers/gpu/drm/radeon/r600.c
> +++ b/drivers/gpu/drm/radeon/r600.c
> @@ -4088,16 +4088,15 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
> }
>
> /**
> - * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
> + * r600_mmio_hdp_flush - flush Host Data Path cache via MMIO
> * rdev: radeon device structure
> - * bo: buffer object struct which userspace is waiting for idle
> *
> - * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
> - * through ring buffer, this leads to corruption in rendering, see
> - * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
> - * directly perform HDP flush by writing register through MMIO.
> + * Some R6XX/R7XX don't seem to take into account HDP flushes performed
> + * through the ring buffer. This leads to corruption in rendering, see
> + * http://bugzilla.kernel.org/show_bug.cgi?id=15186 . To avoid this, we
> + * directly perform the HDP flush by writing the register through MMIO.
> */
> -void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
> +void r600_mmio_hdp_flush(struct radeon_device *rdev)
> {
> /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
> * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
> index 6695b62..4a76e13 100644
> --- a/drivers/gpu/drm/radeon/radeon.h
> +++ b/drivers/gpu/drm/radeon/radeon.h
> @@ -1771,13 +1771,8 @@ struct radeon_asic {
> int (*suspend)(struct radeon_device *rdev);
> void (*vga_set_state)(struct radeon_device *rdev, bool state);
> int (*asic_reset)(struct radeon_device *rdev);
> - /* ioctl hw specific callback. Some hw might want to perform special
> - * operation on specific ioctl. For instance on wait idle some hw
> - * might want to perform and HDP flush through MMIO as it seems that
> - * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
> - * through ring.
> - */
> - void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
> + /* Flush the HDP cache via MMIO */
> + void (*mmio_hdp_flush)(struct radeon_device *rdev);
> /* check if 3D engine is idle */
> bool (*gui_idle)(struct radeon_device *rdev);
> /* wait for mc_idle */
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
> index 34b9aa9..ba8caa7 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.c
> +++ b/drivers/gpu/drm/radeon/radeon_asic.c
> @@ -194,7 +194,7 @@ static struct radeon_asic r100_asic = {
> .resume = &r100_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &r100_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &r100_mc_wait_for_idle,
> .gart = {
> @@ -260,7 +260,7 @@ static struct radeon_asic r200_asic = {
> .resume = &r100_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &r100_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &r100_mc_wait_for_idle,
> .gart = {
> @@ -340,7 +340,7 @@ static struct radeon_asic r300_asic = {
> .resume = &r300_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &r300_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &r300_mc_wait_for_idle,
> .gart = {
> @@ -406,7 +406,7 @@ static struct radeon_asic r300_asic_pcie = {
> .resume = &r300_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &r300_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &r300_mc_wait_for_idle,
> .gart = {
> @@ -472,7 +472,7 @@ static struct radeon_asic r420_asic = {
> .resume = &r420_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &r300_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &r300_mc_wait_for_idle,
> .gart = {
> @@ -538,7 +538,7 @@ static struct radeon_asic rs400_asic = {
> .resume = &rs400_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &r300_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &rs400_mc_wait_for_idle,
> .gart = {
> @@ -604,7 +604,7 @@ static struct radeon_asic rs600_asic = {
> .resume = &rs600_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &rs600_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &rs600_mc_wait_for_idle,
> .gart = {
> @@ -672,7 +672,7 @@ static struct radeon_asic rs690_asic = {
> .resume = &rs690_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &rs600_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &rs690_mc_wait_for_idle,
> .gart = {
> @@ -740,7 +740,7 @@ static struct radeon_asic rv515_asic = {
> .resume = &rv515_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &rs600_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &rv515_mc_wait_for_idle,
> .gart = {
> @@ -806,7 +806,7 @@ static struct radeon_asic r520_asic = {
> .resume = &r520_resume,
> .vga_set_state = &r100_vga_set_state,
> .asic_reset = &rs600_asic_reset,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r100_gui_idle,
> .mc_wait_for_idle = &r520_mc_wait_for_idle,
> .gart = {
> @@ -898,7 +898,7 @@ static struct radeon_asic r600_asic = {
> .resume = &r600_resume,
> .vga_set_state = &r600_vga_set_state,
> .asic_reset = &r600_asic_reset,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &r600_mc_wait_for_idle,
> .get_xclk = &r600_get_xclk,
> @@ -970,7 +970,7 @@ static struct radeon_asic rv6xx_asic = {
> .resume = &r600_resume,
> .vga_set_state = &r600_vga_set_state,
> .asic_reset = &r600_asic_reset,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &r600_mc_wait_for_idle,
> .get_xclk = &r600_get_xclk,
> @@ -1060,7 +1060,7 @@ static struct radeon_asic rs780_asic = {
> .resume = &r600_resume,
> .vga_set_state = &r600_vga_set_state,
> .asic_reset = &r600_asic_reset,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &r600_mc_wait_for_idle,
> .get_xclk = &r600_get_xclk,
> @@ -1163,7 +1163,7 @@ static struct radeon_asic rv770_asic = {
> .resume = &rv770_resume,
> .asic_reset = &r600_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &r600_mc_wait_for_idle,
> .get_xclk = &rv770_get_xclk,
> @@ -1281,7 +1281,7 @@ static struct radeon_asic evergreen_asic = {
> .resume = &evergreen_resume,
> .asic_reset = &evergreen_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &rv770_get_xclk,
> @@ -1373,7 +1373,7 @@ static struct radeon_asic sumo_asic = {
> .resume = &evergreen_resume,
> .asic_reset = &evergreen_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &r600_get_xclk,
> @@ -1464,7 +1464,7 @@ static struct radeon_asic btc_asic = {
> .resume = &evergreen_resume,
> .asic_reset = &evergreen_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &rv770_get_xclk,
> @@ -1599,7 +1599,7 @@ static struct radeon_asic cayman_asic = {
> .resume = &cayman_resume,
> .asic_reset = &cayman_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &rv770_get_xclk,
> @@ -1699,7 +1699,7 @@ static struct radeon_asic trinity_asic = {
> .resume = &cayman_resume,
> .asic_reset = &cayman_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &r600_get_xclk,
> @@ -1829,7 +1829,7 @@ static struct radeon_asic si_asic = {
> .resume = &si_resume,
> .asic_reset = &si_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = r600_ioctl_wait_idle,
> + .mmio_hdp_flush = r600_mmio_hdp_flush,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &si_get_xclk,
> @@ -1987,7 +1987,7 @@ static struct radeon_asic ci_asic = {
> .resume = &cik_resume,
> .asic_reset = &cik_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &cik_get_xclk,
> @@ -2091,7 +2091,7 @@ static struct radeon_asic kv_asic = {
> .resume = &cik_resume,
> .asic_reset = &cik_asic_reset,
> .vga_set_state = &r600_vga_set_state,
> - .ioctl_wait_idle = NULL,
> + .mmio_hdp_flush = NULL,
> .gui_idle = &r600_gui_idle,
> .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
> .get_xclk = &cik_get_xclk,
> diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
> index f632e31..b8826c6 100644
> --- a/drivers/gpu/drm/radeon/radeon_asic.h
> +++ b/drivers/gpu/drm/radeon/radeon_asic.h
> @@ -351,7 +351,7 @@ void r600_hpd_fini(struct radeon_device *rdev);
> bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
> void r600_hpd_set_polarity(struct radeon_device *rdev,
> enum radeon_hpd_id hpd);
> -extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
> +extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
> extern bool r600_gui_idle(struct radeon_device *rdev);
> extern void r600_pm_misc(struct radeon_device *rdev);
> extern void r600_pm_init_profile(struct radeon_device *rdev);
> diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
> index 08756f6..a350cf9 100644
> --- a/drivers/gpu/drm/radeon/radeon_gem.c
> +++ b/drivers/gpu/drm/radeon/radeon_gem.c
> @@ -366,9 +366,9 @@ int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
> }
> robj = gem_to_radeon_bo(gobj);
> r = radeon_bo_wait(robj, NULL, false);
> - /* callback hw specific functions if any */
> - if (rdev->asic->ioctl_wait_idle)
> - robj->rdev->asic->ioctl_wait_idle(rdev, robj);
> + /* Flush HDP cache via MMIO if necessary */
> + if (rdev->asic->mmio_hdp_flush)
> + robj->rdev->asic->mmio_hdp_flush(rdev);
> drm_gem_object_unreference_unlocked(gobj);
> r = radeon_gem_handle_lockup(rdev, r);
> return r;
> --
> 2.0.1
>
> _______________________________________________
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
More information about the dri-devel
mailing list