[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=73378

--- Comment #4 from Alex Deucher <agd5f at yahoo.com> ---
(In reply to comment #3)
> same problem here. UVD is initialised properly but setting clocks timesout.

If this is a regression, can you bisect?

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