[PATCH v2 1/2] drm/nouveau/fb/nv50: Add PFB writes

[Pierre Moreau]

(This is a v2 of patch "drm/nouveau/disp/nv50: Add PFB writes")

This fix a GPU lockup on 9400M (NVAC) when using acceleration, see
https://bugs.freedesktop.org/show_bug.cgi?id=27501

v2:
- Move code to subdev/fb/nv50.c as suggested by Roy Spliet;
- Remove arbitrary writes to 100c18/100c24 as suggested by Roy Spliet;
- Replace write to 100c1c of arbitrary value by the address of a scratch page
  as proposed by Ilia Mirkin;
- Remove enabling of bits 16 and 0 as they don't yield in any changes.

Signed-off-by: Pierre Moreau <pierre.morrow at free.fr>
---
 drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
index 4150b0d..5c84d13 100644
--- a/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/subdev/fb/nv50.c
@@ -289,6 +289,17 @@ nv50_fb_init(struct nouveau_object *object)
 	if (ret)
 		return ret;
 
+	/* Not a clue what this is exactly. Without enabling bit 1 of
+	 * 100c14, system will lockup while initialising the card
+	 * (#27501)
+	 */
+	if (nv_device(priv)->chipset == 0xac) {
+		if ((nv_rd32(priv, 0x100c14) & 0x00000002) == 0x00000000) {
+			nv_wr32(priv, 0x100c1c, priv->r100c08 >> 8);
+			nv_mask(priv, 0x100c14, 0x00000000, 0x00000002);
+		}
+	}
+
 	/* Not a clue what this is exactly.  Without pointing it at a
 	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
 	 * cause IOMMU "read from address 0" errors (rh#561267)
-- 
2.1.2