[Mesa-dev] [PATCH] drm/radeon: Add RADEON_GEM_CPU_ACCESS BO creation flag

[Alex Deucher]

On Mon, Sep 8, 2014 at 9:15 PM, Michel Dänzer <michel at daenzer.net> wrote:
> On 09.09.2014 09:47, Michel Dänzer wrote:
>> On 09.09.2014 02:36, Alex Deucher wrote:
>>>
>>> Updated version with comments integrated.
>>
>> [...]
>>
>>> @@ -314,10 +314,12 @@ int radeon_bo_pin_restricted(struct radeon_bo
>>> *bo, u32 domain, u64 max_offset,
>>>          unsigned lpfn = 0;
>>>
>>>          /* force to pin into visible video ram */
>>> -        if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
>>> -            lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
>>> -        else
>>> +        if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) {
>>> +            if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS))
>>> +                lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
>>> +        } else {
>>>              lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
>>> +        }
>>
>> The else block can be removed as well, but that can be done in another
>> patch.
>
> Actually, I just noticed a problem, the following if statement:
>
>>               if (max_offset)
>>                       lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
>
> This will ignore max_offset if lpfn is 0. So either go with v1 of this hunk,
> or rebase on top of the patch below.
>

Rebased on your patch and attached.

Alex

>
> From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer at amd.com>
> Date: Tue, 9 Sep 2014 10:09:23 +0900
> Subject: [PATCH] drm/radeon: Clean up assignment of TTM placement lpfn member
>  for pinning
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
> ---
>  drivers/gpu/drm/radeon/radeon_object.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
> index 908ea541..8ec8150 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -307,18 +307,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
>         }
>         radeon_ttm_placement_from_domain(bo, domain);
>         for (i = 0; i < bo->placement.num_placement; i++) {
> -               unsigned lpfn = 0;
> -
>                 /* force to pin into visible video ram */
>                 if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
> -                       lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
> +                       bo->placements[i].lpfn =
> +                               min(bo->rdev->mc.visible_vram_size, max_offset)
> +                               >> PAGE_SHIFT;
>                 else
> -                       lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
> -
> -               if (max_offset)
> -                       lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
> +                       bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
>
> -               bo->placements[i].lpfn = lpfn;
>                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
>         }
>
> --
> 2.1.0
>
>
> --
> Earthling Michel Dänzer            |                  http://www.amd.com
> Libre software enthusiast          |                Mesa and X developer
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