[Bug 83708] [vdpau,uvd] kernel oops, Unable to handle kernel paging request at virtual address

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=83708

--- Comment #6 from Jack <zduo006 at 163.com> ---
(In reply to comment #1)
> (In reply to comment #1)
> > Hi, I try to using gpu hardware accelerate to play video from mplayer
> > (vdpau+uvd)  . The machine architecture is sparc64,video card is radeon
> > HD7450,OS version is redhat7,kernel version is 3.10.0, mplayer version is
> > 1.1-21,mesa version is 9.2.5-6.
> 
> Please attach the output of dmesg (showing at least all radeon driver
> related initialization), the /var/log/Xorg.0.log file and the output of
> vdpauinfo.
> 
> Can you try newer versions of the kernel and Mesa?
> 
> P.S. AFAICT the 7450 is Northern Islands generation (Caicos) based, not
> Southern Islands based, otherwise I'd be very surprised you even got this
> far, given bug 82455. :)

Hi, attachment are the logs of xort,radeon init,vdpauinfo, the output seem to
be ok.

I try to trace the code ,found that it execute  radeon_uvd_cs_reloc func to get
the start address of the relocs in GPU RAM.
 reloc = p->relocs_ptr[idx/4]     (idx is 0)
 start = reloc->lobj.gpu_offset
and the start address is start:0x182c000, the radeon_uvd_cs_msg func can remap
the gpu address to cpu virtual address use radeon_bo_kmap(bo,
&ptr)->ttm_bo_ioremap, the return cpu virtual address is  [zd
radeon_uvd_cs_msg]  ptr:000000ca1182c000, msg:000000ca1182c000. and this
address is the unhandle address, see the error log. 
       I try to change the PAGE_SHIFT to 12(gpu page shift) in the
ttm_bo_ioremap(cpu is 8K page size ,gpu is 4K page size) ,but no effects. I
think the bo store in gpu ram has the wrong gpu_offset.But I don't know the
reason. the only way can effect this is the remap,base the different cpu page
size and gpu page size.
       Can give me any idea about this? Or maybe have some ways to  verified?
Tks
       By the way, where can download the document about the ttm and gem ? I am
puzzled about the principle of gpu memory managerment .

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