[PATCH 2/3] drm/exynos: reset temporary value after write to register

[Joonyoung Shim]

Hi Gustavo,

On 03/19/2015 11:27 PM, Gustavo Padovan wrote:
> From: Gustavo Padovan <gustavo.padovan at collabora.co.uk>
> 
> 'val' wasn't clean after its last usage, so we could get garbage value and
> send the wrong command to the hw.
> 
> Signed-off-by: Gustavo Padovan <gustavo.padovan at collabora.co.uk>
> ---
>  drivers/gpu/drm/exynos/exynos_mixer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
> index a95fe84..7aff88f 100644
> --- a/drivers/gpu/drm/exynos/exynos_mixer.c
> +++ b/drivers/gpu/drm/exynos/exynos_mixer.c
> @@ -687,7 +687,7 @@ static void mixer_win_reset(struct mixer_context *ctx)
>  	mixer_reg_write(res, MXR_GRAPHIC_CFG(0), val);
>  
>  	/* Blend layer 1 into layer 0 */
> -	val |= MXR_GRP_CFG_BLEND_PRE_MUL;

I know this is not wrong, current code means layer 1 needs above
register setting value of layer 0 as default.

Thanks.

> +	val = MXR_GRP_CFG_BLEND_PRE_MUL;
>  	val |= MXR_GRP_CFG_PIXEL_BLEND_EN;
>  	mixer_reg_write(res, MXR_GRAPHIC_CFG(1), val);
>  
>