[PATCH 1/2] drm/panel: simple: Add bus format for HannStar HSD070PWW1 LVDS panel
thierry.reding at gmail.com
Fri Aug 7 06:22:55 PDT 2015
On Fri, Aug 07, 2015 at 03:06:38PM +0200, Philipp Zabel wrote:
> Am Freitag, den 07.08.2015, 14:42 +0200 schrieb Thierry Reding:
> > On Fri, Jun 26, 2015 at 12:27:08PM +0200, Lucas Stach wrote:
> > > From: Philipp Zabel <p.zabel at pengutronix.de>
> > >
> > Can you be more specific here? What kind of bus format is this?
> The bus_format contains more information than just the bpc. In this
> case, the SPWG default format for RGB666 via 3-pair LVDS specifies how
> the 18 color bits are serialized in the 7 time slots for each pixel
> clock. See
> for details.
> > Why is it that .bpc = 6 doesn't work here?
> In this case a LVDS driver could indeed still decide itself that
> bpc == 6 should be translated to MEDIA_BUS_FMT_RGB666_1X7X3_SPWG (and
> not MEDIA_BUS_FMT_RGB666_1X18, or MEDIA_BUS_FMT_RGB666_1X24_CPADHI, for
> example). But in the bpc == 8 case there are two different standard ways
> to order the bits (SPWG/VESA vs JEIDA).
> For consistency, I'd prefer to set bus_format to the correct value
Now if we can put that into a commit message, that'd be perfect.
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