drm/msm/dsi: hs_zero timing
werner.johansson at gmail.com
Sun Aug 23 23:17:11 PDT 2015
On Sat, Aug 22, 2015 at 6:25 AM, Rob Clark <robdclark at gmail.com> wrote:
> fwiw, if the values are related to the physical cabling/wiring, rather
> than the panel timing, we should probably get them from DT..
> if a combination of the timing and the wiring, that gets a bit more complicated
> (I am not actually sure myself about these)
Right, I don't see it being possible to calculate the timing
differences between lanes from any panel mode timing. There are some
dependencies to the length of calculated hs_zero and hs_prepare
values, depending on how these per-lane adjustments are setup, but it
would be safe to assume that if the per-lane values need tweaking
(from DT possibly) then you would have to know the details of the DSI
timing anyway, so that shouldn't pose much of a problem.
The description of the 5 bits in the CFG4 register isn't entirely
clear, the value in bit 0-3, possibly scaled by a factor of 16(?), has
to be less than the hs_prepare register if bit 4 is set or less than
the hs_zero register if bit 4 is clear.
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