[PATCH] drm/radeon: Don't try to enable write-combining without PAT

[Alex Deucher]

On Wed, Feb 4, 2015 at 4:49 AM, Christian König <deathsimple at vodafone.de> wrote:
> Am 04.02.2015 um 02:19 schrieb Michel Dänzer:
>>
>> From: Michel Dänzer <michel.daenzer at amd.com>
>>
>> Doing so can cause things to become slow.
>>
>> Print a warning at compile time and an informative message at runtime in
>> that case.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88758
>> Cc: stable at vger.kernel.org
>> Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
>
>
> Interesting I wonder what the rational behind this is. I mean CONFIG_X86_PAT
> will obviously affect write combining, but why does it slow down things if
> we request something that the kernel isn't configured for?
>
> Anyway, patch is Reviewed-by: Christian König <christian.koenig at amd.com>

Applied to my 3.20 tree.

Thanks!

Alex

>
> Regards,
> Christian.
>
>
>> ---
>>   drivers/gpu/drm/radeon/radeon_object.c | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/radeon/radeon_object.c
>> b/drivers/gpu/drm/radeon/radeon_object.c
>> index 7d68223..bd3df10 100644
>> --- a/drivers/gpu/drm/radeon/radeon_object.c
>> +++ b/drivers/gpu/drm/radeon/radeon_object.c
>> @@ -238,6 +238,18 @@ int radeon_bo_create(struct radeon_device *rdev,
>>          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
>>          */
>>         bo->flags &= ~RADEON_GEM_GTT_WC;
>> +#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
>> +       /* Don't try to enable write-combining when it can't work, or
>> things
>> +        * may be slow
>> +        * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
>> +        */
>> +
>> +#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better
>> performance \
>> +        thanks to write-combining
>> +
>> +       DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
>> +                     "better performance thanks to write-combining\n");
>> +       bo->flags &= ~RADEON_GEM_GTT_WC;
>>   #endif
>>         radeon_ttm_placement_from_domain(bo, domain);
>
>
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