[RFC PATCH] drm/radeon: program auxch directly
Alex Deucher
alexdeucher at gmail.com
Fri Feb 20 09:41:50 PST 2015
On Thu, Feb 19, 2015 at 7:43 PM, Alex Deucher <alexdeucher at gmail.com> wrote:
> On Thu, Feb 19, 2015 at 6:21 PM, Dave Airlie <airlied at gmail.com> wrote:
>> From: Dave Airlie <airlied at redhat.com>
>>
>> The atombios tables have an unfortunate restriction on only
>> being able to write 12 bytes, MST really wants 16-bytes here,
>> and since the hw can do it, we should just write directly to it.
>>
>> This uses a module option to allow for it now, and maybe
>> we should provide the old code as a fallback for a while.
>>
>> Signed-off-by: Dave Airlie <airlied at redhat.com>
>> ---
>>
>> Just putting this out there for people to know I'm doing it,
>> most likely I'd want to merge on by default for MST systems
>> at least.
>>
>> TODO: testing, irq support?
>
> This code will only work on DCE5+. Things moved around on older
> asics. That said, DCE5 is the first asic that supports MST, so we can
> stick with atom on the older ones. I'm fine with enabling it for DCE5
> and newer by default.
I took a quick pass at cleaning this up. See attached.
Alex
>
>>
>> drivers/gpu/drm/radeon/Makefile | 2 +-
>> drivers/gpu/drm/radeon/atombios_dp.c | 5 +-
>> drivers/gpu/drm/radeon/radeon.h | 3 +
>> drivers/gpu/drm/radeon/radeon_dp_auxch.c | 253 +++++++++++++++++++++++++++++++
>> drivers/gpu/drm/radeon/radeon_drv.c | 4 +
>> 5 files changed, 265 insertions(+), 2 deletions(-)
>> create mode 100644 drivers/gpu/drm/radeon/radeon_dp_auxch.c
>>
>> diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
>> index 4605633..fa635f0 100644
>> --- a/drivers/gpu/drm/radeon/Makefile
>> +++ b/drivers/gpu/drm/radeon/Makefile
>> @@ -81,7 +81,7 @@ radeon-y += radeon_device.o radeon_asic.o radeon_kms.o \
>> rv770_smc.o cypress_dpm.o btc_dpm.o sumo_dpm.o sumo_smc.o trinity_dpm.o \
>> trinity_smc.o ni_dpm.o si_smc.o si_dpm.o kv_smc.o kv_dpm.o ci_smc.o \
>> ci_dpm.o dce6_afmt.o radeon_vm.o radeon_ucode.o radeon_ib.o \
>> - radeon_sync.o radeon_audio.o
>> + radeon_sync.o radeon_audio.o radeon_dp_auxch.o
>>
>> radeon-$(CONFIG_MMU_NOTIFIER) += radeon_mn.o
>>
>> diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
>> index db42a67..37594b2 100644
>> --- a/drivers/gpu/drm/radeon/atombios_dp.c
>> +++ b/drivers/gpu/drm/radeon/atombios_dp.c
>> @@ -223,7 +223,10 @@ void radeon_dp_aux_init(struct radeon_connector *radeon_connector)
>>
>> radeon_connector->ddc_bus->rec.hpd = radeon_connector->hpd.hpd;
>> radeon_connector->ddc_bus->aux.dev = radeon_connector->base.kdev;
>> - radeon_connector->ddc_bus->aux.transfer = radeon_dp_aux_transfer;
>
>>
>
> Rename the old one to radeon_atombios_dp_aux_transfer.
>
> if (ASIC_IS_DCE5(rdev)) {
> if (radeon_auxch)
> radeon_connector->ddc_bus->aux.transfer =
> radeon_dp_aux_transfer_native;
> else
> radeon_connector->ddc_bus->aux.transfer =
> radeon_atombios_dp_aux_transfer;
> } else {
> radeon_connector->ddc_bus->aux.transfer =
> radeon_atombios_dp_aux_transfer;
> }
>
>> ret = drm_dp_aux_register(&radeon_connector->ddc_bus->aux);
>> if (!ret)
>> diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
>> index 5587603..bd4e8bd 100644
>> --- a/drivers/gpu/drm/radeon/radeon.h
>> +++ b/drivers/gpu/drm/radeon/radeon.h
>> @@ -111,6 +111,7 @@ extern int radeon_deep_color;
>> extern int radeon_use_pflipirq;
>> extern int radeon_bapm;
>> extern int radeon_backlight;
>> +extern int radeon_auxch;
>>
>> /*
>> * Copy from radeon_drv.h so we don't have to include both and have conflicting
>> @@ -3112,6 +3113,8 @@ int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
>> uint32_t *vline_start_end,
>> uint32_t *vline_status);
>>
>> +ssize_t
>> +radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
>> #include "radeon_object.h"
>>
>> #endif
>> diff --git a/drivers/gpu/drm/radeon/radeon_dp_auxch.c b/drivers/gpu/drm/radeon/radeon_dp_auxch.c
>> new file mode 100644
>> index 0000000..0cf94e6
>> --- /dev/null
>> +++ b/drivers/gpu/drm/radeon/radeon_dp_auxch.c
>> @@ -0,0 +1,253 @@
>> +/*
>> + * Copyright 2015 Red Hat Inc.
>> + *
>> + * Permission is hereby granted, free of charge, to any person obtaining a
>> + * copy of this software and associated documentation files (the "Software"),
>> + * to deal in the Software without restriction, including without limitation
>> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
>> + * and/or sell copies of the Software, and to permit persons to whom the
>> + * Software is furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
>> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
>> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
>> + * OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> + * Authors: Dave Airlie
>> + */
>> +#include <drm/drmP.h>
>> +#include <drm/radeon_drm.h>
>> +#include "radeon.h"
>> +
>> +/* HW definitions */
>> +#define DP_AUX_CONTROL 0x6200
>> +
>> +#define DP_AUX_CONTROL_AUX_EN (1 << 0)
>> +#define DP_AUX_CONTROL_AUX_LS_READ_EN (1 << 8)
>> +#define DP_AUX_CONTROL_AUX_LS_UPDATE_DISABLE(x) (((x) & 0x1) << 12)
>> +#define DP_AUX_CONTROL_AUX_HPD_DISCON(x) (((x) & 0x1) << 16)
>> +#define DP_AUX_CONTROL_AUX_DET_EN (1 << 18)
>> +#define DP_AUX_CONTROL_AUX_HPD_SEL(x) (((x) & 0x7) << 20)
>> +#define DP_AUX_CONTROL_AUX_IMPCAL_REQ_EN (1 << 24)
>> +#define DP_AUX_CONTROL_AUX_TEST_MODE (1 << 28)
>> +#define DP_AUX_CONTROL_AUX_DEGLITCH_EN (1 << 29)
>> +
>> +#define DP_AUX_SW_CONTROL 0x6204
>> +
>> +#define DP_AUX_SW_GO (1 << 0)
>> +#define DP_AUX_LS_READ_TRIG (1 << 2)
>> +#define DP_AUX_SW_START_DELAY(x) (((x) & 0xf) << 4)
>> +#define DP_AUX_SW_WR_BYTES(x) (((x) & 0x1f) << 16)
>> +
>> +#define DP_AUX_SW_INTERRUPT_CONTROL 0x620c
>> +#define DP_AUX_SW_DONE_INT (1 << 0)
>> +#define DP_AUX_SW_DONE_ACK (1 << 1)
>> +#define DP_AUX_SW_DONE_MASK (1 << 2)
>> +#define DP_AUX_SW_LS_DONE_INT (1 << 4)
>> +#define DP_AUX_SW_LS_DONE_MASK (1 << 6)
>> +
>> +#define DP_AUX_SW_STATUS 0x6210
>> +#define DP_AUX_SW_DONE (1 << 0)
>> +#define DP_AUX_SW_REQ (1 << 1)
>> +#define DP_AUX_SW_RX_TIMEOUT_STATE(x) (((x) & 0x7) << 4)
>> +#define DP_AUX_SW_RX_TIMEOUT (1 << 7)
>> +
>> +#define DP_AUX_SW_RX_OVERFLOW (1 << 8)
>> +#define DP_AUX_SW_RX_HPD_DISCON (1 << 9)
>> +#define DP_AUX_SW_RX_PARTIAL_BYTE (1 << 10)
>> +#define DP_AUX_SW_NON_AUX_MODE (1 << 11)
>> +#define DP_AUX_SW_RX_MIN_COUNT_VIOL (1 << 12)
>> +#define DP_AUX_SW_RX_INVALID_STOP (1 << 14)
>> +#define DP_AUX_SW_RX_SYNC_INVALID_L (1 << 17)
>> +#define DP_AUX_SW_RX_SYNC_INVALID_H (1 << 18)
>> +#define DP_AUX_SW_RX_INVALID_START (1 << 19)
>> +#define DP_AUX_SW_RX_RECV_NO_DET (1 << 20)
>> +#define DP_AUX_SW_RX_RECV_INVALID_H (1 << 22)
>> +#define DP_AUX_SW_RX_RECV_INVALID_V (1 << 23)
>> +
>> +#define DP_AUX_RX_ERROR_FLAGS (DP_AUX_SW_RX_OVERFLOW | \
>> + DP_AUX_SW_RX_HPD_DISCON | \
>> + DP_AUX_SW_RX_PARTIAL_BYTE | \
>> + DP_AUX_SW_NON_AUX_MODE | \
>> + DP_AUX_SW_RX_MIN_COUNT_VIOL | \
>> + DP_AUX_SW_RX_INVALID_STOP | \
>> + DP_AUX_SW_RX_SYNC_INVALID_L | \
>> + DP_AUX_SW_RX_SYNC_INVALID_H | \
>> + DP_AUX_SW_RX_INVALID_START | \
>> + DP_AUX_SW_RX_RECV_NO_DET | \
>> + DP_AUX_SW_RX_RECV_INVALID_H | \
>> + DP_AUX_SW_RX_RECV_INVALID_V)
>> +
>> +#define DP_AUX_SW_REPLY_GET_BYTE_COUNT(x) (((x) >> 24) & 0x1f)
>> +
>> +#define DP_AUX_SW_DATA 0x6218
>> +#define DP_AUX_SW_DATA_RW (1 << 0)
>> +#define DP_AUX_SW_DATA_MASK(x) (((x) & 0xff) << 8)
>> +#define DP_AUX_SW_DATA_INDEX(x) (((x) & 0x1f) << 16)
>> +#define DP_AUX_SW_AUTOINCREMENT_DISABLE (1 << 31)
>> +
>> +#define BARE_ADDRESS_SIZE 3
>> +
>> +/* base addresses */
>> +static uint32_t dce5_dp_base[6] = { 0x6200,
>> + 0x6250,
>> + 0x62a0,
>> + 0x6300,
>> + 0x6350,
>> + 0x63a0 };
>> +
>> +/* native implementation of AUXCH for DCE5 */
>> +#define DPREG(x) (((x) - 0x6200) + offset)
>> +
>
> to be more like the rest of the code, maybe use an instance table? E.g.,
>
> static const u32 aux_offsets[6] =
> {
> 0x6200 - 0x6200,
> 0x6250 - 0x6200,
> 0x62a0 - 0x6200,
> 0x6300 - 0x6200,
> 0x6350 - 0x6200,
> 0x63a0 - 0x6200,
> };
>
> then
>
> WREG32(DP_AUX_CONTROL + aux_offsets[i], tmp);
>
>
>> +ssize_t
>> +radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
>> +{
>> + struct radeon_i2c_chan *chan =
>> + container_of(aux, struct radeon_i2c_chan, aux);
>> + struct drm_device *dev = chan->dev;
>> + struct radeon_device *rdev = dev->dev_private;
>> + int ret = 0, i;
>> + uint32_t tmp, ack = 0;
>> + uint32_t offset = dce5_dp_base[chan->rec.i2c_id & 0xf];
>> + u8 byte;
>> + u8 *buf = msg->buffer;
>> + int retry_count = 0;
>> + int bytes;
>> + int msize;
>> + bool is_write = false;
>> +
>> + if (WARN_ON(msg->size > 16))
>> + return -E2BIG;
>> +
>> + switch (msg->request & ~DP_AUX_I2C_MOT) {
>> + case DP_AUX_NATIVE_WRITE:
>> + case DP_AUX_I2C_WRITE:
>> + is_write = true;
>> + break;
>> + case DP_AUX_NATIVE_READ:
>> + case DP_AUX_I2C_READ:
>> + break;
>> + default:
>> + return -EINVAL;
>> + }
>> +
>> + /* work out two sizes required */
>> + msize = 0;
>> + bytes = BARE_ADDRESS_SIZE;
>> + if (msg->size) {
>> + msize = msg->size - 1;
>> + bytes++;
>> + if (is_write)
>> + bytes += msg->size;
>> + }
>> +
>> + mutex_lock(&chan->mutex);
>> +
>
> You also need to select the pad mode. The register offsets are
> different between DCE versions, but we already track the registers for
> i2c, so we can just use that. E.g.,
>
> tmp = RREG32(chan->rec.mask_clk_reg);
> tmp |= (1 << 16);
> WREG32(chan->rec.mask_clk_reg, tmp);
>
> We already handle switching the pad mode to i2c in amdgpu_i2c_pre_xfer().
>
>
>> + /* setup AUX control register with correct HPD pin */
>> + tmp = RREG32(DPREG(DP_AUX_CONTROL));
>> +
>> + tmp &= DP_AUX_CONTROL_AUX_HPD_SEL(0x7);
>> + tmp |= DP_AUX_CONTROL_AUX_HPD_SEL(chan->rec.hpd);
>> + tmp |= DP_AUX_CONTROL_AUX_EN | DP_AUX_CONTROL_AUX_LS_READ_EN;
>> +
>> + WREG32(DPREG(DP_AUX_CONTROL), tmp);
>> +
>> + /* atombios appears to write this twice lets copy it */
>> + WREG32(DPREG(DP_AUX_SW_CONTROL),
>> + DP_AUX_SW_WR_BYTES(bytes));
>> + WREG32(DPREG(DP_AUX_SW_CONTROL),
>> + DP_AUX_SW_WR_BYTES(bytes));
>> +
>> + /* write the data header into the registers */
>> + /* request, addres, msg size */
>> + byte = (msg->request << 4);
>> + WREG32(DPREG(DP_AUX_SW_DATA),
>> + DP_AUX_SW_DATA_MASK(byte) | DP_AUX_SW_AUTOINCREMENT_DISABLE);
>> +
>> + byte = (msg->address >> 8) & 0xff;
>> + WREG32(DPREG(DP_AUX_SW_DATA),
>> + DP_AUX_SW_DATA_MASK(byte));
>> +
>> + byte = msg->address & 0xff;
>> + WREG32(DPREG(DP_AUX_SW_DATA),
>> + DP_AUX_SW_DATA_MASK(byte));
>> +
>> + byte = msize;
>> + WREG32(DPREG(DP_AUX_SW_DATA),
>> + DP_AUX_SW_DATA_MASK(byte));
>> +
>> + /* if we are writing - write the msg buffer */
>> + if (is_write) {
>> + for (i = 0; i < msg->size; i++) {
>> + WREG32(DPREG(DP_AUX_SW_DATA),
>> + DP_AUX_SW_DATA_MASK(buf[i]));
>> + }
>> + }
>> +
>> + /* clear the ACK */
>> + WREG32(DPREG(DP_AUX_SW_INTERRUPT_CONTROL), DP_AUX_SW_DONE_ACK);
>> +
>> + /* write the size and GO bits */
>> + WREG32(DPREG(DP_AUX_SW_CONTROL),
>> + DP_AUX_SW_WR_BYTES(bytes) | DP_AUX_SW_GO);
>> +
>> + /* poll the status registers - TODO irq support */
>> + do {
>> + tmp = RREG32(DPREG(DP_AUX_SW_STATUS));
>> + if (tmp & DP_AUX_SW_DONE) {
>> + break;
>> + }
>> + usleep_range(100, 200);
>> + } while (retry_count++ < 1000);
>> +
>> + if (retry_count >= 1000) {
>> + DRM_ERROR("auxch hw never signalled completion, error %08x\n", tmp);
>> + ret = -EIO;
>> + goto done;
>> + }
>> +
>> + if (tmp & DP_AUX_SW_RX_TIMEOUT) {
>> + DRM_DEBUG_KMS("dp_aux_ch timed out\n");
>> + ret = -ETIMEDOUT;
>> + goto done;
>> + }
>> + if (tmp & DP_AUX_RX_ERROR_FLAGS) {
>> + DRM_DEBUG_KMS("dp_aux_ch flags not zero: %08x\n", tmp);
>> + ret = -EIO;
>> + goto done;
>> + }
>> +
>> + bytes = DP_AUX_SW_REPLY_GET_BYTE_COUNT(tmp);
>> + if (bytes) {
>> + WREG32(DPREG(DP_AUX_SW_DATA),
>> + DP_AUX_SW_DATA_RW | DP_AUX_SW_AUTOINCREMENT_DISABLE);
>> +
>> + tmp = RREG32(DPREG(DP_AUX_SW_DATA));
>> + ack = (tmp >> 8) & 0xff;
>> +
>> + for (i = 0; i < bytes - 1; i++) {
>> + tmp = RREG32(DPREG(DP_AUX_SW_DATA));
>> + if (buf)
>> + buf[i] = (tmp >> 8) & 0xff;
>> + }
>> + if (buf)
>> + ret = bytes - 1;
>> + }
>> +
>> + WREG32(DPREG(DP_AUX_SW_INTERRUPT_CONTROL), DP_AUX_SW_DONE_ACK);
>> +
>> + if (is_write)
>> + ret = msg->size;
>> +done:
>> + mutex_unlock(&chan->mutex);
>> +
>> + if (ret >= 0)
>> + msg->reply = ack >> 4;
>> + return ret;
>> +}
>> diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
>> index 5d684be..0141ce3 100644
>> --- a/drivers/gpu/drm/radeon/radeon_drv.c
>> +++ b/drivers/gpu/drm/radeon/radeon_drv.c
>> @@ -190,6 +190,7 @@ int radeon_deep_color = 0;
>> int radeon_use_pflipirq = 2;
>> int radeon_bapm = -1;
>> int radeon_backlight = -1;
>> +int radeon_auxch = 0;
>>
>> MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
>> module_param_named(no_wb, radeon_no_wb, int, 0444);
>> @@ -275,6 +276,9 @@ module_param_named(bapm, radeon_bapm, int, 0444);
>> MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
>> module_param_named(backlight, radeon_backlight, int, 0444);
>>
>> +MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable)");
>> +module_param_named(auxch, radeon_auxch, int, 0444);
>> +
>> static struct pci_device_id pciidlist[] = {
>> radeon_PCI_IDS
>> };
>> --
>> 2.1.0
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/dri-devel
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