atombios_crtc.c - make error messages distinguishable "unable to allocate a PPLL\n"
Alexander.Deucher at amd.com
Mon Jun 8 10:43:31 PDT 2015
> -----Original Message-----
> From: James Feeney [mailto:james at nurealm.net]
> Sent: Monday, June 08, 2015 1:10 PM
> To: Koenig, Christian; Deucher, Alexander
> Cc: dri-devel at lists.freedesktop.org
> Subject: Re: atombios_crtc.c - make error messages distinguishable "unable
> to allocate a PPLL\n"
> > Actually it's always the same error. The message just appears in that file
> > multiple times for different hardware generations.
> Which is fine, presupposing that the user already knows what hardware
> they are using _and_ how the video card manufacturer actually implemented
> display interfaces, as, for instance, whether or not the "external PLL" really
> exists, or was left off. That is "presuming the conclusion", though. The user
> does _not_ know.
> The problem is that the error message is not informative for the person who
> actually encountering the problem. At that point, the user already knows
> their display is not working, and they do not need an error message that
> effectively, "Your display is not working." That is insulting. They need
> information about how to respond, how to "fix" the problem. The idea is to
> able to look at the source code.
> For instance, I have an HD 5570 card, including a DisplayPort interface, for
> which we can read "The 5000-series designs host two internal clocks and one
> external clock." With exactly three clocks and three displays, there should
> _never_ be an allocation error. Instead, there are constant "unable to
> a PPLL" errors, generated in the fifth "/* all other cases */" code path. Why?
DCE4 parts (like the 5570) only have an external clock if the OEM supplied it, hence not all boards have it. Also, the external clock source can only be used to drive native DP (DisplayPort), not non-DP outputs like DVI or HDMI or VGA or a passive DP to DVI/HDMI convertor. If you are using 3 non-DP displays, that will only work if at least two of the displays have the exact same clock and hence can share a PLL. If you want to use a the external clock, the board has to have it, and if it does, it can only be used for DP. There are lots of other complex cases and limitations as well depending on the asic.
> I had to modify and recompile the source just to find where the error was
> generated. Please make life a little easier.
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