[PATCH] staging: imx-drm: Fix pixel clock polarity

[David Jander]

clk_pol should almost always be 1 (active-high pixel clock). When using the
LDB, it must be 1 and for externally connected displays it should most
probably also be 1. Original Freescale code sets this bit always, except
when the FB_SYNC_CLK_LAT_FALL flag is set, which is a proprietary extension
from Freescale that is not normally set.

Signed-off-by: David Jander <david at protonic.nl>
---
 drivers/gpu/drm/imx/ipuv3-crtc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/imx/ipuv3-crtc.c b/drivers/gpu/drm/imx/ipuv3-crtc.c
index 7425fcc..97799ff 100644
--- a/drivers/gpu/drm/imx/ipuv3-crtc.c
+++ b/drivers/gpu/drm/imx/ipuv3-crtc.c
@@ -173,7 +173,7 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 		sig_cfg.clkflags = 0;
 
 	sig_cfg.enable_pol = 1;
-	sig_cfg.clk_pol = 0;
+	sig_cfg.clk_pol = 1;
 	sig_cfg.bus_format = ipu_crtc->bus_format;
 	sig_cfg.v_to_h_sync = 0;
 	sig_cfg.hsync_pin = ipu_crtc->di_hsync_pin;
-- 
2.1.4