[PATCH 09/12] intel: Provide IS_GENX() macros taking a drm_intel_device as argument
Damien Lespiau
damien.lespiau at intel.com
Thu Mar 5 08:20:17 PST 2015
Time to switch over all the IS_GENX() macros to the new device object.
Nothing more than a mechanical search & replace here.
Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
intel/intel_bufmgr_gem.c | 7 +-
intel/intel_chipset.h | 158 ----------------------------------------------
intel/intel_decode.c | 41 ++++++------
intel/intel_device_priv.h | 8 +++
4 files changed, 31 insertions(+), 183 deletions(-)
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 58543a2..011fa5b 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -3451,8 +3451,7 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
bufmgr_gem->pci_device = drm_intel_device_get_devid(bufmgr_gem->dev);
bufmgr_gem->gen = bufmgr_gem->dev->gen;
- if (IS_GEN3(bufmgr_gem->pci_device) &&
- bufmgr_gem->gtt_size > 256*1024*1024) {
+ if (IS_GEN3(bufmgr_gem->dev) && bufmgr_gem->gtt_size > 256*1024*1024) {
/* The unmappable part of gtt on gen 3 (i.e. above 256MB) can't
* be used for tiled blits. To simplify the accounting, just
* substract the unmappable part (fixed to 256MB on all known
@@ -3494,8 +3493,8 @@ drm_intel_bufmgr_gem_init(int fd, int batch_size)
/* Kernel does not supports HAS_LLC query, fallback to GPU
* generation detection and assume that we have LLC on GEN6/7
*/
- bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->pci_device) ||
- IS_GEN7(bufmgr_gem->pci_device);
+ bufmgr_gem->has_llc = IS_GEN6(bufmgr_gem->dev) ||
+ IS_GEN7(bufmgr_gem->dev);
} else
bufmgr_gem->has_llc = *gp.value;
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 241d700..134c877 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -181,162 +181,4 @@
#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
-#define IS_ILD(devid) ((devid) == PCI_CHIP_ILD_G)
-#define IS_ILM(devid) ((devid) == PCI_CHIP_ILM_G)
-
-#define IS_915(devid) ((devid) == PCI_CHIP_I915_G || \
- (devid) == PCI_CHIP_E7221_G || \
- (devid) == PCI_CHIP_I915_GM)
-
-#define IS_945GM(devid) ((devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME)
-
-#define IS_945(devid) ((devid) == PCI_CHIP_I945_G || \
- (devid) == PCI_CHIP_I945_GM || \
- (devid) == PCI_CHIP_I945_GME || \
- IS_G33(devid))
-
-#define IS_G33(devid) ((devid) == PCI_CHIP_G33_G || \
- (devid) == PCI_CHIP_Q33_G || \
- (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_GEN2(devid) ((devid) == PCI_CHIP_I830_M || \
- (devid) == PCI_CHIP_845_G || \
- (devid) == PCI_CHIP_I855_GM || \
- (devid) == PCI_CHIP_I865_G)
-
-#define IS_GEN3(devid) (IS_945(devid) || IS_915(devid))
-
-#define IS_GEN5(devid) (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_GEN6(devid) ((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
- (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
- (devid) == PCI_CHIP_SANDYBRIDGE_S)
-
-#define IS_GEN7(devid) (IS_IVYBRIDGE(devid) || \
- IS_HASWELL(devid) || \
- IS_VALLEYVIEW(devid))
-
-#define IS_IVYBRIDGE(devid) ((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
- (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
- (devid) == PCI_CHIP_IVYBRIDGE_S || \
- (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
-
-#define IS_VALLEYVIEW(devid) ((devid) == PCI_CHIP_VALLEYVIEW_PO || \
- (devid) == PCI_CHIP_VALLEYVIEW_1 || \
- (devid) == PCI_CHIP_VALLEYVIEW_2 || \
- (devid) == PCI_CHIP_VALLEYVIEW_3)
-
-#define IS_HSW_GT1(devid) ((devid) == PCI_CHIP_HASWELL_GT1 || \
- (devid) == PCI_CHIP_HASWELL_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_E_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
- (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
-#define IS_HSW_GT2(devid) ((devid) == PCI_CHIP_HASWELL_GT2 || \
- (devid) == PCI_CHIP_HASWELL_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_E_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
- (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
-#define IS_HSW_GT3(devid) ((devid) == PCI_CHIP_HASWELL_GT3 || \
- (devid) == PCI_CHIP_HASWELL_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_E_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
- (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
-
-#define IS_HASWELL(devid) (IS_HSW_GT1(devid) || \
- IS_HSW_GT2(devid) || \
- IS_HSW_GT3(devid))
-
-#define IS_BROADWELL(devid) (((devid & 0xff00) != 0x1600) ? 0 : \
- (((devid & 0x00f0) >> 4) > 3) ? 0 : \
- ((devid & 0x000f) == BDW_SPARE) ? 1 : \
- ((devid & 0x000f) == BDW_ULT) ? 1 : \
- ((devid & 0x000f) == BDW_IRIS) ? 1 : \
- ((devid & 0x000f) == BDW_SERVER) ? 1 : \
- ((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
- ((devid & 0x000f) == BDW_ULX) ? 1 : 0)
-
-#define IS_CHERRYVIEW(devid) ((devid) == PCI_CHIP_CHERRYVIEW_0 || \
- (devid) == PCI_CHIP_CHERRYVIEW_1 || \
- (devid) == PCI_CHIP_CHERRYVIEW_2 || \
- (devid) == PCI_CHIP_CHERRYVIEW_3)
-
-#define IS_GEN8(devid) (IS_BROADWELL(devid) || \
- IS_CHERRYVIEW(devid))
-
-#define IS_SKL_GT1(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_ULX_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_DT_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT1 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT1)
-
-#define IS_SKL_GT2(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_ULT_GT2F || \
- (devid) == PCI_CHIP_SKYLAKE_ULX_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_DT_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT2 || \
- (devid) == PCI_CHIP_SKYLAKE_WKS_GT2)
-
-#define IS_SKL_GT3(devid) ((devid) == PCI_CHIP_SKYLAKE_ULT_GT3 || \
- (devid) == PCI_CHIP_SKYLAKE_HALO_GT3 || \
- (devid) == PCI_CHIP_SKYLAKE_SRV_GT3)
-
-#define IS_SKYLAKE(devid) (IS_SKL_GT1(devid) || \
- IS_SKL_GT2(devid) || \
- IS_SKL_GT3(devid))
-
-#define IS_GEN9(devid) IS_SKYLAKE(devid)
-
#endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index 2fd2cc5..abe689c 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -35,7 +35,7 @@
#include "libdrm.h"
#include "xf86drm.h"
-#include "intel_device.h"
+#include "intel_device_priv.h"
#include "intel_chipset.h"
#include "intel_bufmgr.h"
@@ -1277,7 +1277,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
const char *format, *zformat, *type;
uint32_t opcode;
uint32_t *data = ctx->data;
- uint32_t devid = ctx->devid;
+ struct drm_intel_device *dev = ctx->dev;
struct {
uint32_t opcode;
@@ -1353,7 +1353,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
for (word = 0; word <= 8; word++) {
if (data[0] & (1 << (4 + word))) {
/* save vertex state for decode */
- if (!IS_GEN2(devid)) {
+ if (!IS_GEN2(dev)) {
int tex_num;
if (word == 2) {
@@ -2029,7 +2029,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
}
return len;
case 0x01:
- if (IS_GEN2(devid))
+ if (IS_GEN2(dev))
break;
instr_out(ctx, 0, "3DSTATE_SAMPLER_STATE\n");
instr_out(ctx, 1, "mask\n");
@@ -2254,7 +2254,7 @@ decode_3d_1d(struct drm_intel_decode *ctx)
for (idx = 0; idx < ARRAY_SIZE(opcodes_3d_1d); idx++) {
opcode_3d_1d = &opcodes_3d_1d[idx];
- if (opcode_3d_1d->i830_only && !IS_GEN2(devid))
+ if (opcode_3d_1d->i830_only && !IS_GEN2(dev))
continue;
if (((data[0] & 0x00ff0000) >> 16) == opcode_3d_1d->opcode) {
@@ -3144,7 +3144,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
unsigned int i, j, sba_len;
const char *desc1 = NULL;
uint32_t *data = ctx->data;
- uint32_t devid = ctx->devid;
+ struct drm_intel_device *dev = ctx->dev;
struct {
uint32_t opcode;
@@ -3297,9 +3297,9 @@ decode_3d_965(struct drm_intel_decode *ctx)
instr_out(ctx, 0, "STATE_BASE_ADDRESS\n");
i++;
- if (IS_GEN6(devid) || IS_GEN7(devid))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
sba_len = 10;
- else if (IS_GEN5(devid))
+ else if (IS_GEN5(dev))
sba_len = 8;
else
sba_len = 6;
@@ -3308,17 +3308,17 @@ decode_3d_965(struct drm_intel_decode *ctx)
state_base_out(ctx, i++, "general");
state_base_out(ctx, i++, "surface");
- if (IS_GEN6(devid) || IS_GEN7(devid))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
state_base_out(ctx, i++, "dynamic");
state_base_out(ctx, i++, "indirect");
- if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
+ if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
state_base_out(ctx, i++, "instruction");
state_max_out(ctx, i++, "general");
- if (IS_GEN6(devid) || IS_GEN7(devid))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
state_max_out(ctx, i++, "dynamic");
state_max_out(ctx, i++, "indirect");
- if (IS_GEN5(devid) || IS_GEN6(devid) || IS_GEN7(devid))
+ if (IS_GEN5(dev) || IS_GEN6(dev) || IS_GEN7(dev))
state_max_out(ctx, i++, "instruction");
return len;
@@ -3387,7 +3387,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
for (i = 1; i < len;) {
int idx, access;
- if (IS_GEN6(devid)) {
+ if (IS_GEN6(dev)) {
idx = 26;
access = 20;
} else {
@@ -3414,8 +3414,8 @@ decode_3d_965(struct drm_intel_decode *ctx)
instr_out(ctx, i,
"buffer %d: %svalid, type 0x%04x, "
"src offset 0x%04x bytes\n",
- data[i] >> ((IS_GEN6(devid) || IS_GEN7(devid)) ? 26 : 27),
- data[i] & (1 << ((IS_GEN6(devid) || IS_GEN7(devid)) ? 25 : 26)) ?
+ data[i] >> ((IS_GEN6(dev) || IS_GEN7(dev)) ? 26 : 27),
+ data[i] & (1 << ((IS_GEN6(dev) || IS_GEN7(dev)) ? 25 : 26)) ?
"" : "in", (data[i] >> 16) & 0x1ff,
data[i] & 0x07ff);
i++;
@@ -3599,7 +3599,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
case 0x7905:
instr_out(ctx, 0, "3DSTATE_DEPTH_BUFFER\n");
- if (IS_GEN5(devid) || IS_GEN6(devid))
+ if (IS_GEN5(dev) || IS_GEN6(dev))
instr_out(ctx, 1,
"%s, %s, pitch = %d bytes, %stiled, HiZ %d, Seperate Stencil %d\n",
get_965_surfacetype(data[1] >> 29),
@@ -3623,7 +3623,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
if (len >= 6)
instr_out(ctx, 5, "\n");
if (len >= 7) {
- if (IS_GEN6(devid))
+ if (IS_GEN6(dev))
instr_out(ctx, 6, "\n");
else
instr_out(ctx, 6,
@@ -3633,7 +3633,7 @@ decode_3d_965(struct drm_intel_decode *ctx)
return len;
case 0x7a00:
- if (IS_GEN6(devid) || IS_GEN7(devid)) {
+ if (IS_GEN6(dev) || IS_GEN7(dev)) {
unsigned int i;
if (len != 4 && len != 5)
fprintf(out, "Bad count in PIPE_CONTROL\n");
@@ -3893,9 +3893,9 @@ drm_intel_decode(struct drm_intel_decode *ctx)
{
int ret;
unsigned int index = 0;
- uint32_t devid;
int size = ctx->base_count * 4;
void *temp;
+ struct drm_intel_device *dev = ctx->dev;
if (!ctx)
return;
@@ -3912,7 +3912,6 @@ drm_intel_decode(struct drm_intel_decode *ctx)
ctx->hw_offset = ctx->base_hw_offset;
ctx->count = ctx->base_count;
- devid = ctx->devid;
head_offset = ctx->head;
tail_offset = ctx->tail;
out = ctx->out;
@@ -3951,7 +3950,7 @@ drm_intel_decode(struct drm_intel_decode *ctx)
case 0x3:
if (ctx->dev->gen >= 4)
index += decode_3d_965(ctx);
- else if (IS_GEN3(devid))
+ else if (IS_GEN3(dev))
index += decode_3d(ctx);
else
index += decode_3d_i830(ctx);
diff --git a/intel/intel_device_priv.h b/intel/intel_device_priv.h
index 87dc1dc..d1bc523 100644
--- a/intel/intel_device_priv.h
+++ b/intel/intel_device_priv.h
@@ -31,5 +31,13 @@
* header, hence a _priv.h one for internal use.
*/
#define IS_CHIP(dev, id) ((dev)->chip == DRM_INTEL_CHIP_ ## id)
+#define IS_GEN2(dev) ((dev)->gen == 2)
+#define IS_GEN3(dev) ((dev)->gen == 3)
+#define IS_GEN4(dev) ((dev)->gen == 4)
+#define IS_GEN5(dev) ((dev)->gen == 5)
+#define IS_GEN6(dev) ((dev)->gen == 6)
+#define IS_GEN7(dev) ((dev)->gen == 7)
+#define IS_GEN8(dev) ((dev)->gen == 8)
+#define IS_GEN9(dev) ((dev)->gen == 9)
#endif /* __INTEL_DEVICE_PRIV_H__ */
--
1.8.3.1
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