[PATCH 12/12] intel: Remove intel_chipset.h
Damien Lespiau
damien.lespiau at intel.com
Thu Mar 5 08:20:20 PST 2015
Finally, we can remove this file now that everything is using
drm_intel_device.
Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
intel/Makefile.sources | 1 -
intel/intel_bufmgr_gem.c | 1 -
intel/intel_chipset.h | 184 -----------------------------------------------
intel/intel_decode.c | 1 -
4 files changed, 187 deletions(-)
delete mode 100644 intel/intel_chipset.h
diff --git a/intel/Makefile.sources b/intel/Makefile.sources
index 2f8398b..b58ca4f 100644
--- a/intel/Makefile.sources
+++ b/intel/Makefile.sources
@@ -8,7 +8,6 @@ LIBDRM_INTEL_FILES := \
intel_device.c \
intel_device.h \
intel_device_priv.h \
- intel_chipset.h \
mm.c \
mm.h
diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
index 011fa5b..d0119fc 100644
--- a/intel/intel_bufmgr_gem.c
+++ b/intel/intel_bufmgr_gem.c
@@ -61,7 +61,6 @@
#include "intel_bufmgr.h"
#include "intel_bufmgr_priv.h"
#include "intel_device_priv.h"
-#include "intel_chipset.h"
#include "intel_aub.h"
#include "string.h"
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
deleted file mode 100644
index 134c877..0000000
--- a/intel/intel_chipset.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- *
- * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- */
-
-#ifndef _INTEL_CHIPSET_H
-#define _INTEL_CHIPSET_H
-
-#define PCI_CHIP_I810 0x7121
-#define PCI_CHIP_I810_DC100 0x7123
-#define PCI_CHIP_I810_E 0x7125
-#define PCI_CHIP_I815 0x1132
-
-#define PCI_CHIP_I830_M 0x3577
-#define PCI_CHIP_845_G 0x2562
-#define PCI_CHIP_I855_GM 0x3582
-#define PCI_CHIP_I865_G 0x2572
-
-#define PCI_CHIP_I915_G 0x2582
-#define PCI_CHIP_E7221_G 0x258A
-#define PCI_CHIP_I915_GM 0x2592
-#define PCI_CHIP_I945_G 0x2772
-#define PCI_CHIP_I945_GM 0x27A2
-#define PCI_CHIP_I945_GME 0x27AE
-
-#define PCI_CHIP_Q35_G 0x29B2
-#define PCI_CHIP_G33_G 0x29C2
-#define PCI_CHIP_Q33_G 0x29D2
-
-#define PCI_CHIP_IGD_GM 0xA011
-#define PCI_CHIP_IGD_G 0xA001
-
-#define IS_IGDGM(devid) ((devid) == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid) ((devid) == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
-
-#define PCI_CHIP_I965_G 0x29A2
-#define PCI_CHIP_I965_Q 0x2992
-#define PCI_CHIP_I965_G_1 0x2982
-#define PCI_CHIP_I946_GZ 0x2972
-#define PCI_CHIP_I965_GM 0x2A02
-#define PCI_CHIP_I965_GME 0x2A12
-
-#define PCI_CHIP_GM45_GM 0x2A42
-
-#define PCI_CHIP_IGD_E_G 0x2E02
-#define PCI_CHIP_Q45_G 0x2E12
-#define PCI_CHIP_G45_G 0x2E22
-#define PCI_CHIP_G41_G 0x2E32
-
-#define PCI_CHIP_ILD_G 0x0042
-#define PCI_CHIP_ILM_G 0x0046
-
-#define PCI_CHIP_SANDYBRIDGE_GT1 0x0102 /* desktop */
-#define PCI_CHIP_SANDYBRIDGE_GT2 0x0112
-#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS 0x0122
-#define PCI_CHIP_SANDYBRIDGE_M_GT1 0x0106 /* mobile */
-#define PCI_CHIP_SANDYBRIDGE_M_GT2 0x0116
-#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS 0x0126
-#define PCI_CHIP_SANDYBRIDGE_S 0x010A /* server */
-
-#define PCI_CHIP_IVYBRIDGE_GT1 0x0152 /* desktop */
-#define PCI_CHIP_IVYBRIDGE_GT2 0x0162
-#define PCI_CHIP_IVYBRIDGE_M_GT1 0x0156 /* mobile */
-#define PCI_CHIP_IVYBRIDGE_M_GT2 0x0166
-#define PCI_CHIP_IVYBRIDGE_S 0x015a /* server */
-#define PCI_CHIP_IVYBRIDGE_S_GT2 0x016a /* server */
-
-#define PCI_CHIP_HASWELL_GT1 0x0402 /* Desktop */
-#define PCI_CHIP_HASWELL_GT2 0x0412
-#define PCI_CHIP_HASWELL_GT3 0x0422
-#define PCI_CHIP_HASWELL_M_GT1 0x0406 /* Mobile */
-#define PCI_CHIP_HASWELL_M_GT2 0x0416
-#define PCI_CHIP_HASWELL_M_GT3 0x0426
-#define PCI_CHIP_HASWELL_S_GT1 0x040A /* Server */
-#define PCI_CHIP_HASWELL_S_GT2 0x041A
-#define PCI_CHIP_HASWELL_S_GT3 0x042A
-#define PCI_CHIP_HASWELL_B_GT1 0x040B /* Reserved */
-#define PCI_CHIP_HASWELL_B_GT2 0x041B
-#define PCI_CHIP_HASWELL_B_GT3 0x042B
-#define PCI_CHIP_HASWELL_E_GT1 0x040E /* Reserved */
-#define PCI_CHIP_HASWELL_E_GT2 0x041E
-#define PCI_CHIP_HASWELL_E_GT3 0x042E
-#define PCI_CHIP_HASWELL_SDV_GT1 0x0C02 /* Desktop */
-#define PCI_CHIP_HASWELL_SDV_GT2 0x0C12
-#define PCI_CHIP_HASWELL_SDV_GT3 0x0C22
-#define PCI_CHIP_HASWELL_SDV_M_GT1 0x0C06 /* Mobile */
-#define PCI_CHIP_HASWELL_SDV_M_GT2 0x0C16
-#define PCI_CHIP_HASWELL_SDV_M_GT3 0x0C26
-#define PCI_CHIP_HASWELL_SDV_S_GT1 0x0C0A /* Server */
-#define PCI_CHIP_HASWELL_SDV_S_GT2 0x0C1A
-#define PCI_CHIP_HASWELL_SDV_S_GT3 0x0C2A
-#define PCI_CHIP_HASWELL_SDV_B_GT1 0x0C0B /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_B_GT2 0x0C1B
-#define PCI_CHIP_HASWELL_SDV_B_GT3 0x0C2B
-#define PCI_CHIP_HASWELL_SDV_E_GT1 0x0C0E /* Reserved */
-#define PCI_CHIP_HASWELL_SDV_E_GT2 0x0C1E
-#define PCI_CHIP_HASWELL_SDV_E_GT3 0x0C2E
-#define PCI_CHIP_HASWELL_ULT_GT1 0x0A02 /* Desktop */
-#define PCI_CHIP_HASWELL_ULT_GT2 0x0A12
-#define PCI_CHIP_HASWELL_ULT_GT3 0x0A22
-#define PCI_CHIP_HASWELL_ULT_M_GT1 0x0A06 /* Mobile */
-#define PCI_CHIP_HASWELL_ULT_M_GT2 0x0A16
-#define PCI_CHIP_HASWELL_ULT_M_GT3 0x0A26
-#define PCI_CHIP_HASWELL_ULT_S_GT1 0x0A0A /* Server */
-#define PCI_CHIP_HASWELL_ULT_S_GT2 0x0A1A
-#define PCI_CHIP_HASWELL_ULT_S_GT3 0x0A2A
-#define PCI_CHIP_HASWELL_ULT_B_GT1 0x0A0B /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_B_GT2 0x0A1B
-#define PCI_CHIP_HASWELL_ULT_B_GT3 0x0A2B
-#define PCI_CHIP_HASWELL_ULT_E_GT1 0x0A0E /* Reserved */
-#define PCI_CHIP_HASWELL_ULT_E_GT2 0x0A1E
-#define PCI_CHIP_HASWELL_ULT_E_GT3 0x0A2E
-#define PCI_CHIP_HASWELL_CRW_GT1 0x0D02 /* Desktop */
-#define PCI_CHIP_HASWELL_CRW_GT2 0x0D12
-#define PCI_CHIP_HASWELL_CRW_GT3 0x0D22
-#define PCI_CHIP_HASWELL_CRW_M_GT1 0x0D06 /* Mobile */
-#define PCI_CHIP_HASWELL_CRW_M_GT2 0x0D16
-#define PCI_CHIP_HASWELL_CRW_M_GT3 0x0D26
-#define PCI_CHIP_HASWELL_CRW_S_GT1 0x0D0A /* Server */
-#define PCI_CHIP_HASWELL_CRW_S_GT2 0x0D1A
-#define PCI_CHIP_HASWELL_CRW_S_GT3 0x0D2A
-#define PCI_CHIP_HASWELL_CRW_B_GT1 0x0D0B /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_B_GT2 0x0D1B
-#define PCI_CHIP_HASWELL_CRW_B_GT3 0x0D2B
-#define PCI_CHIP_HASWELL_CRW_E_GT1 0x0D0E /* Reserved */
-#define PCI_CHIP_HASWELL_CRW_E_GT2 0x0D1E
-#define PCI_CHIP_HASWELL_CRW_E_GT3 0x0D2E
-#define BDW_SPARE 0x2
-#define BDW_ULT 0x6
-#define BDW_SERVER 0xa
-#define BDW_IRIS 0xb
-#define BDW_WORKSTATION 0xd
-#define BDW_ULX 0xe
-
-#define PCI_CHIP_VALLEYVIEW_PO 0x0f30 /* VLV PO board */
-#define PCI_CHIP_VALLEYVIEW_1 0x0f31
-#define PCI_CHIP_VALLEYVIEW_2 0x0f32
-#define PCI_CHIP_VALLEYVIEW_3 0x0f33
-
-#define PCI_CHIP_CHERRYVIEW_0 0x22b0
-#define PCI_CHIP_CHERRYVIEW_1 0x22b1
-#define PCI_CHIP_CHERRYVIEW_2 0x22b2
-#define PCI_CHIP_CHERRYVIEW_3 0x22b3
-
-#define PCI_CHIP_SKYLAKE_ULT_GT2 0x1916
-#define PCI_CHIP_SKYLAKE_ULT_GT1 0x1906
-#define PCI_CHIP_SKYLAKE_ULT_GT3 0x1926
-#define PCI_CHIP_SKYLAKE_ULT_GT2F 0x1921
-#define PCI_CHIP_SKYLAKE_ULX_GT1 0x190E
-#define PCI_CHIP_SKYLAKE_ULX_GT2 0x191E
-#define PCI_CHIP_SKYLAKE_DT_GT2 0x1912
-#define PCI_CHIP_SKYLAKE_DT_GT1 0x1902
-#define PCI_CHIP_SKYLAKE_HALO_GT2 0x191B
-#define PCI_CHIP_SKYLAKE_HALO_GT3 0x192B
-#define PCI_CHIP_SKYLAKE_HALO_GT1 0x190B
-#define PCI_CHIP_SKYLAKE_SRV_GT2 0x191A
-#define PCI_CHIP_SKYLAKE_SRV_GT3 0x192A
-#define PCI_CHIP_SKYLAKE_SRV_GT1 0x190A
-#define PCI_CHIP_SKYLAKE_WKS_GT2 0x191D
-
-#endif /* _INTEL_CHIPSET_H */
diff --git a/intel/intel_decode.c b/intel/intel_decode.c
index abe689c..d2e6934 100644
--- a/intel/intel_decode.c
+++ b/intel/intel_decode.c
@@ -36,7 +36,6 @@
#include "libdrm.h"
#include "xf86drm.h"
#include "intel_device_priv.h"
-#include "intel_chipset.h"
#include "intel_bufmgr.h"
/* Struct for tracking drm_intel_decode state. */
--
1.8.3.1
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