[PATCH libdrm] radeon: Handle surface offsets exceeding 32 bits correctly
Michel Dänzer
michel at daenzer.net
Tue Nov 10 01:27:55 PST 2015
From: Michel Dänzer <michel.daenzer at amd.com>
The slice_size and bo_size fields were getting truncated to 32 bits.
Signed-off-by: Michel Dänzer <michel.daenzer at amd.com>
---
radeon/radeon_surface.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
index fad4bda..5ec9745 100644
--- a/radeon/radeon_surface.c
+++ b/radeon/radeon_surface.c
@@ -163,7 +163,7 @@ static void surf_minify(struct radeon_surface *surf,
struct radeon_surface_level *surflevel,
unsigned bpe, unsigned level,
uint32_t xalign, uint32_t yalign, uint32_t zalign,
- unsigned offset)
+ uint64_t offset)
{
surflevel->npix_x = mip_minify(surf->npix_x, level);
surflevel->npix_y = mip_minify(surf->npix_y, level);
@@ -184,7 +184,7 @@ static void surf_minify(struct radeon_surface *surf,
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
- surflevel->slice_size = surflevel->pitch_bytes * surflevel->nblk_y;
+ surflevel->slice_size = (uint64_t)surflevel->pitch_bytes * surflevel->nblk_y;
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
}
@@ -570,7 +570,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
unsigned mtilew,
unsigned mtileh,
unsigned mtileb,
- unsigned offset)
+ uint64_t offset)
{
unsigned mtile_pr, mtile_ps;
@@ -598,7 +598,7 @@ static void eg_surf_minify(struct radeon_surface *surf,
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
- surflevel->slice_size = mtile_ps * mtileb * slice_pt;
+ surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
}
@@ -1415,7 +1415,7 @@ static void si_surf_minify(struct radeon_surface *surf,
struct radeon_surface_level *surflevel,
unsigned bpe, unsigned level,
uint32_t xalign, uint32_t yalign, uint32_t zalign,
- uint32_t slice_align, unsigned offset)
+ uint32_t slice_align, uint64_t offset)
{
if (level == 0) {
surflevel->npix_x = surf->npix_x;
@@ -1453,7 +1453,8 @@ static void si_surf_minify(struct radeon_surface *surf,
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
- surflevel->slice_size = ALIGN(surflevel->pitch_bytes * surflevel->nblk_y, slice_align);
+ surflevel->slice_size = ALIGN((uint64_t)surflevel->pitch_bytes * surflevel->nblk_y,
+ (uint64_t)slice_align);
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
}
@@ -1462,7 +1463,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
struct radeon_surface_level *surflevel,
unsigned bpe, unsigned level, unsigned slice_pt,
uint32_t xalign, uint32_t yalign, uint32_t zalign,
- unsigned mtileb, unsigned offset)
+ unsigned mtileb, uint64_t offset)
{
unsigned mtile_pr, mtile_ps;
@@ -1501,7 +1502,7 @@ static void si_surf_minify_2d(struct radeon_surface *surf,
mtile_ps = (mtile_pr * surflevel->nblk_y) / yalign;
surflevel->offset = offset;
surflevel->pitch_bytes = surflevel->nblk_x * bpe * surf->nsamples;
- surflevel->slice_size = mtile_ps * mtileb * slice_pt;
+ surflevel->slice_size = (uint64_t)mtile_ps * mtileb * slice_pt;
surf->bo_size = offset + surflevel->slice_size * surflevel->nblk_z * surf->array_size;
}
--
2.6.2
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