[Intel-gfx] [PATCH 2/2] drm/i915/skl: Add support for pipe background color
Bob Paauwe
bob.j.paauwe at intel.com
Wed Nov 18 13:43:46 PST 2015
On Thu, 22 Oct 2015 17:25:35 -0700
Matt Roper <matthew.d.roper at intel.com> wrote:
> SKL and BXT allow CRTC's to be programmed with a background/canvas color
> below the programmable planes. Let's expose this as a property to allow
> userspace to program a desired value.
>
> This patch is based on earlier work by Chandra Konduru; unfortunately
> the driver has evolved so much since his patches were written
> (pre-atomic) that the functionality had to be pretty much completely
> rewritten for the new i915 atomic internals.
>
> Cc: Chandra Konduru <chandra.konduru at intel.com>
> Cc: dri-devel at lists.freedesktop.org
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> ---
> Documentation/DocBook/gpu.tmpl | 10 ++++++++-
> drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 10 +++++++++
> drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++++++++++++++++++++
> 4 files changed, 71 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/DocBook/gpu.tmpl b/Documentation/DocBook/gpu.tmpl
> index c05d7df..40c0d49 100644
> --- a/Documentation/DocBook/gpu.tmpl
> +++ b/Documentation/DocBook/gpu.tmpl
> @@ -2819,7 +2819,7 @@ void intel_crt_init(struct drm_device *dev)
> <td valign="top" >TBD</td>
> </tr>
> <tr>
> - <td rowspan="20" valign="top" >i915</td>
> + <td rowspan="21" valign="top" >i915</td>
> <td rowspan="2" valign="top" >Generic</td>
> <td valign="top" >"Broadcast RGB"</td>
> <td valign="top" >ENUM</td>
> @@ -2835,6 +2835,14 @@ void intel_crt_init(struct drm_device *dev)
> <td valign="top" >TBD</td>
> </tr>
> <tr>
> + <td rowspan="1" valign="top" >CRTC</td>
> + <td valign="top" >“background_color”</td>
> + <td valign="top" >RGBA</td>
> + <td valign="top" > </td>
> + <td valign="top" >CRTC</td>
> + <td valign="top" >Background color of regions not covered by a plane</td>
> + </tr>
> + <tr>
> <td rowspan="17" valign="top" >SDVO-TV</td>
> <td valign="top" >“mode”</td>
> <td valign="top" >ENUM</td>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index a3b22bd..acb05e5 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2977,6 +2977,15 @@ static int i915_display_info(struct seq_file *m, void *unused)
> crtc->base.cursor->state->crtc_h,
> crtc->cursor_addr, yesno(active));
> }
> + if (INTEL_INFO(dev)->gen >= 9 && pipe_config->base.active) {
> + drm_rgba_t background = pipe_config->base.background_color;
> +
> + seq_printf(m, "\tbackground color (10bpc): r=%x g=%x b=%x\n",
> + background.v,
> + DRM_RGBA_REDBITS(background, 10),
> + DRM_RGBA_GREENBITS(background, 10),
> + DRM_RGBA_BLUEBITS(background, 10));
> + }
>
> seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
> yesno(!crtc->cpu_fifo_underrun_disabled),
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9ebf032..95ea394 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7562,6 +7562,16 @@ enum skl_disp_power_wells {
> #define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
> #define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
>
> +/* Skylake pipe bottom color */
> +#define _PIPE_BOTTOM_COLOR_A 0x70034
> +#define _PIPE_BOTTOM_COLOR_B 0x71034
> +#define _PIPE_BOTTOM_COLOR_C 0x72034
> +#define PIPE_BOTTOM_GAMMA_ENABLE (1 << 31)
> +#define PIPE_BOTTOM_CSC_ENABLE (1 << 30)
> +#define PIPE_BOTTOM_COLOR_MASK 0x3FFFFFFF
> +#define PIPE_BOTTOM_COLOR(pipe) _PIPE3(pipe, _PIPE_BOTTOM_COLOR_A, \
> + _PIPE_BOTTOM_COLOR_B, _PIPE_BOTTOM_COLOR_C)
> +
> /* MIPI DSI registers */
>
> #define _MIPI_PORT(port, a, c) _PORT3(port, a, 0, c) /* ports A and C only */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1fc1d24..b00fca9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3332,6 +3332,8 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
> struct drm_i915_private *dev_priv = dev->dev_private;
> struct intel_crtc_state *pipe_config =
> to_intel_crtc_state(crtc->base.state);
> + drm_rgba_t background = pipe_config->base.background_color;
> + uint32_t val;
>
> /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
> crtc->base.mode = crtc->base.state->mode;
> @@ -3368,6 +3370,26 @@ static void intel_update_pipe_config(struct intel_crtc *crtc,
> else if (old_crtc_state->pch_pfit.enabled)
> ironlake_pfit_disable(crtc, true);
> }
> +
> + if (INTEL_INFO(dev)->gen >= 9) {
> + /* BGR 16bpc ==> RGB 10bpc */
> + val = DRM_RGBA_REDBITS(background, 10) << 20
> + | DRM_RGBA_GREENBITS(background, 10) << 10
> + | DRM_RGBA_BLUEBITS(background, 10);
> +
> + /*
> + * Set CSC and gamma for bottom color.
> + *
> + * FIXME: We turn these on unconditionally for now to match
> + * how we've setup the various planes. Once the color
> + * management framework lands, it may or may not choose to
> + * set these bits.
> + */
> + val |= PIPE_BOTTOM_CSC_ENABLE;
> + val |= PIPE_BOTTOM_GAMMA_ENABLE;
> +
> + I915_WRITE(PIPE_BOTTOM_COLOR(crtc->pipe), val);
> + }
> }
>
> static void intel_fdi_normal_train(struct drm_crtc *crtc)
> @@ -11788,6 +11810,9 @@ static int intel_crtc_atomic_check(struct drm_crtc *crtc,
> pipe_config);
> }
>
> + if (crtc->state->background_color.v != crtc_state->background_color.v)
> + pipe_config->update_pipe = true;
> +
> return ret;
> }
>
> @@ -13230,6 +13255,7 @@ static const struct drm_crtc_funcs intel_crtc_funcs = {
> .set_config = drm_atomic_helper_set_config,
> .destroy = intel_crtc_destroy,
> .page_flip = intel_crtc_page_flip,
> + .set_property = drm_atomic_helper_crtc_set_property,
> .atomic_duplicate_state = intel_crtc_duplicate_state,
> .atomic_destroy_state = intel_crtc_destroy_state,
> };
> @@ -13780,6 +13806,19 @@ static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_cr
> scaler_state->scaler_id = -1;
> }
>
> +static void intel_create_background_color_property(struct drm_device *dev,
> + struct intel_crtc *crtc)
> +{
> + if (!dev->mode_config.prop_background_color)
> + dev->mode_config.prop_background_color =
> + drm_mode_create_background_color_property(dev);
> + if (!dev->mode_config.prop_background_color)
> + return;
> +
> + drm_object_attach_property(&crtc->base.base,
> + dev->mode_config.prop_background_color, 0);
This only works because right now drm_rgba_t can represent black as 0,
but you're not honoring the abstraction. What if black really needed
to have alpha set or drm_rgba_t expands to more than 16 bits per color
or we just want to initialize the background color to something other
than black?
> +}
> +
> static void intel_crtc_init(struct drm_device *dev, int pipe)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
> @@ -13855,6 +13894,10 @@ static void intel_crtc_init(struct drm_device *dev, int pipe)
> drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
>
> WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
> +
> + if (INTEL_INFO(dev)->gen >= 9)
> + intel_create_background_color_property(dev, intel_crtc);
> +
> return;
>
> fail:
--
--
Bob Paauwe
Bob.J.Paauwe at intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
More information about the dri-devel
mailing list