[PATCH] checkpatch cleaning no structure changes

[BryanSPaul]

---
 drivers/gpu/drm/amd/amdgpu/vi.c | 41 ++++++++++++++++-------------------------
 1 file changed, 16 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index 6e76c7e..015cdae 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -192,8 +192,7 @@ static void vi_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
 	spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
 }
 
-static const u32 tonga_mgcg_cgcg_init[] =
-{
+static const u32 tonga_mgcg_cgcg_init[] = {
 	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 	mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 	mmPCIE_DATA, 0x000f0000, 0x00000000,
@@ -203,8 +202,7 @@ static const u32 tonga_mgcg_cgcg_init[] =
 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };
 
-static const u32 fiji_mgcg_cgcg_init[] =
-{
+static const u32 fiji_mgcg_cgcg_init[] = {
 	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 	mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 	mmPCIE_DATA, 0x000f0000, 0x00000000,
@@ -214,8 +212,7 @@ static const u32 fiji_mgcg_cgcg_init[] =
 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };
 
-static const u32 iceland_mgcg_cgcg_init[] =
-{
+static const u32 iceland_mgcg_cgcg_init[] = {
 	mmPCIE_INDEX, 0xffffffff, ixPCIE_CNTL2,
 	mmPCIE_DATA, 0x000f0000, 0x00000000,
 	mmSMC_IND_INDEX_4, 0xffffffff, ixCGTT_ROM_CLK_CTRL0,
@@ -223,8 +220,7 @@ static const u32 iceland_mgcg_cgcg_init[] =
 	mmHDP_XDP_CGTT_BLK_CTRL, 0xc0000fff, 0x00000104,
 };
 
-static const u32 cz_mgcg_cgcg_init[] =
-{
+static const u32 cz_mgcg_cgcg_init[] = {
 	mmCGTT_DRM_CLK_CTRL0, 0xffffffff, 0x00600100,
 	mmPCIE_INDEX, 0xffffffff, 0x0140001c,
 	mmPCIE_DATA, 0x000f0000, 0x00000000,
@@ -308,6 +304,7 @@ void vi_srbm_select(struct amdgpu_device *adev,
 		     u32 me, u32 pipe, u32 queue, u32 vmid)
 {
 	u32 srbm_gfx_cntl = 0;
+
 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, PIPEID, pipe);
 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, MEID, me);
 	srbm_gfx_cntl = REG_SET_FIELD(srbm_gfx_cntl, SRBM_GFX_CNTL, VMID, vmid);
@@ -696,8 +693,8 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
 	/* disable CG/PG */
 
 	/* stop the rlc */
-	//XXX
-	//gfx_v8_0_rlc_stop(adev);
+	/*XXX*/
+	/*gfx_v8_0_rlc_stop(adev);*/
 
 	/* Disable GFX parsing/prefetching */
 	tmp = RREG32(mmCP_ME_CNTL);
@@ -726,9 +723,8 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
 	}
 
 	gmc_v8_0_mc_stop(adev, &save);
-	if (amdgpu_asic_wait_for_mc_idle(adev)) {
+	if (amdgpu_asic_wait_for_mc_idle(adev))
 		dev_warn(adev->dev, "Wait for MC idle timedout !\n");
-	}

 	if (reset_mask & (AMDGPU_RESET_GFX | AMDGPU_RESET_COMPUTE | AMDGPU_RESET_CP)) {
 		grbm_soft_reset =
@@ -790,7 +786,7 @@ static void vi_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
 
 	if (!(adev->flags & AMD_IS_APU)) {
 		if (reset_mask & AMDGPU_RESET_MC)
-		srbm_soft_reset =
+			srbm_soft_reset =
 			REG_SET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_MC, 1);
 	}
@@ -876,16 +872,15 @@ static void vi_gpu_pci_config_reset(struct amdgpu_device *adev)
 	/* XXX other engines? */
 
 	/* halt the rlc, disable cp internal ints */
-	//XXX
-	//gfx_v8_0_rlc_stop(adev);
+	/*XXX*/
+	/*gfx_v8_0_rlc_stop(adev);*/
 
 	udelay(50);
 
 	/* disable mem access */
 	gmc_v8_0_mc_stop(adev, &save);
-	if (amdgpu_asic_wait_for_mc_idle(adev)) {
+	if (amdgpu_asic_wait_for_mc_idle(adev))
 		dev_warn(adev->dev, "Wait for MC idle timed out !\n");
-	}
 	/* disable BM */
 	pci_clear_master(adev->pdev);
@@ -1049,8 +1044,7 @@ static void vi_enable_doorbell_aperture(struct amdgpu_device *adev,
 }
 /* topaz has no DCE, UVD, VCE */
-static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
-{
+static const struct amdgpu_ip_block_version topaz_ip_blocks[] = {
 	/* ORDER MATTERS! */
 	{
 		.type = AMD_IP_BLOCK_TYPE_COMMON,
@@ -1096,8 +1090,7 @@ static const struct amdgpu_ip_block_version topaz_ip_blocks[] =
 	},
 };
-static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
-{
+static const struct amdgpu_ip_block_version tonga_ip_blocks[] = {
 	/* ORDER MATTERS! */
 	{
 		.type = AMD_IP_BLOCK_TYPE_COMMON,
@@ -1164,8 +1157,7 @@ static const struct amdgpu_ip_block_version tonga_ip_blocks[] =
 	},
 };
-static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
-{
+static const struct amdgpu_ip_block_version fiji_ip_blocks[] = {
 	/* ORDER MATTERS! */
 	{
 		.type = AMD_IP_BLOCK_TYPE_COMMON,
@@ -1232,8 +1224,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] =
 	},
 };
-static const struct amdgpu_ip_block_version cz_ip_blocks[] =
-{
+static const struct amdgpu_ip_block_version cz_ip_blocks[] = {
 	/* ORDER MATTERS! */
 	{
 		.type = AMD_IP_BLOCK_TYPE_COMMON,
-- 
2.4.6