[PATCH] drm/fsl-dcu: Fix endian issue when using clk_register_divider

[Meng Yi]

>  	fsl_dev->pix_clk = clk_register_divider(dev, pix_clk_name,
>  			pix_clk_in_name, 0, base + DCU_DIV_RATIO,
> -			0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);
> +			24, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL);

Tested-by: Meng Yi <meng.yi at nxp.com>

On LS1021A-TWR board.

>  	if (IS_ERR(fsl_dev->pix_clk)) {
>  		dev_err(dev, "failed to register pix clk\n");
>  		ret = PTR_ERR(fsl_dev->pix_clk);