[RFC 2/2] gpu: ipu-v3: reset DMFC memory when disabling

[Philipp Zabel]

Reset the write FIFO memories after disabling the DMFC
to make sure no stale data is kept around.

Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
 drivers/gpu/ipu-v3/ipu-dmfc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/ipu-v3/ipu-dmfc.c b/drivers/gpu/ipu-v3/ipu-dmfc.c
index a40f211..e1e5506 100644
--- a/drivers/gpu/ipu-v3/ipu-dmfc.c
+++ b/drivers/gpu/ipu-v3/ipu-dmfc.c
@@ -131,8 +131,10 @@ void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
 
 	priv->use_count--;
 
-	if (!priv->use_count)
+	if (!priv->use_count) {
 		ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
+		ipu_memory_reset(priv->ipu, IPU_RST_MEM_DMFC_WR);
+	}
 
 	if (priv->use_count < 0)
 		priv->use_count = 0;
-- 
2.8.1