[PATCH 1/2] drm/etnaviv: fail probe if core or bus clock are absent

[Russell King - ARM Linux]

On Mon, Aug 29, 2016 at 12:47:20PM +0200, Lucas Stach wrote:
> Core, bus and shader are all module input clocks. If the SoC integration
> provides the same clock for all inputs, the DT should reflect this by
> supplying the same clock for all 3 inputs.

You're making an assertion that we don't know is true.  There is no
evidence that the GC600 has three input clocks.  Just because iMX
Vivante GPUs have three clocks does not mean that all Vivante IP has
three clock inputs.

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