[PATCH] drm/mxsfb: fix pixel clock polarity

Stefan Agner stefan at agner.ch
Thu Dec 8 00:27:06 UTC 2016

The DRM subsystem specifies the pixel clock polarity from a
controllers perspective: DRM_BUS_FLAG_PIXDATA_NEGEDGE means
the controller drives the data on pixel clocks falling edge.
That is the controllers DOTCLK_POL=0 (Default is data launched
at negative edge).

Also change the data enable logic to be high active by default
and only change if explicitly requested via bus_flags. With
that defaults are:
- Data enable: high active
- Pixel clock polarity: controller drives data on negative edge

Signed-off-by: Stefan Agner <stefan at agner.ch>
Hi Marek,

I discovered this while testing on a i.MX 7 eLCDIF IP. Particularly the
non-standard DE polarity was causing issues. I was using a EDT display
which is part of simple panel driver since a while now and does not
specify any bus_flags currently... Of course I could (and probably should)
add the proper bus_flags there too, but there are several displays
which do not specify any polarity and likely rely on sensible driver
standards (which is afact high active for the DE signal).


 drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 0818903..4bcc8a3 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -168,9 +168,16 @@ static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
 		vdctrl0 |= VDCTRL0_HSYNC_ACT_HIGH;
 	if (m->flags & DRM_MODE_FLAG_PVSYNC)
 		vdctrl0 |= VDCTRL0_VSYNC_ACT_HIGH;
-	if (bus_flags & DRM_BUS_FLAG_DE_HIGH)
+	/* Data Enable should be high active by default */
+	if (!(bus_flags & DRM_BUS_FLAG_DE_LOW))
 		vdctrl0 |= VDCTRL0_ENABLE_ACT_HIGH;
+	/*
+	 * Note: DRM_BUS_FLAG_PIXDATA defines are controller centric,
+	 * controllers VDCTRL0_DOTCLK is display centric.
+	 * Drive on positive edige      -> display samples on falling edge
+	 */
 	writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);

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