[PATCH 1/5] drm/amdgpu/gfx8: fix priv reg interrupt enable

[Christian König]

Am 20.02.2016 um 00:17 schrieb Alex Deucher:
> Looks like a copy/paste typo.
>
> Noticed-by: David Panariti <David.Panariti at amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher at amd.com>

I'm not so deep into the pm stuff, but that all looks reasonable to me.

Whole set is Reviewed-by: Christian König <christian.koenig at amd.com>

Regards,
Christian.

> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index 8f8ec37..1c40bd9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -4995,7 +4995,7 @@ static int gfx_v8_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>   	case AMDGPU_IRQ_STATE_ENABLE:
>   		cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0);
>   		cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
> -					    PRIV_REG_INT_ENABLE, 0);
> +					    PRIV_REG_INT_ENABLE, 1);
>   		WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl);
>   		break;
>   	default: