omap4: how to get the HDMI core IRQ?

[Hans Verkuil]

Hi Tomi,

I hope you (or someone else on this list) can help me find the problem in this code.

I am working on a kernel framework for HDMI CEC (see https://lwn.net/Articles/680942/).
In order to get as much experience with different devices as possible I am trying to
implement it on my omap4430 Pandaboard. The big problem I am facing is that the CEC
interrupts come in through the HDMI_IRQ_CORE interrupt, and that just refuses to
trigger.

The code below adds support for this core interrupt and it is supposed to trigger it
using the Software Induced interrupt to keep the code as simple as possible.

On boot I get this debug line from the pr_info in my code:

irqstat 02000000 wp_irq 06000001 raw 20010000 intr_state 00000001 intr1 00000080 unmask1 00000080 intr_ctrl 0000000a

As far as I can see everything looks perfectly fine, except for the fact that bit 0
of the irqstat is stubbornly 0.

This is using kernel 4.5 with only this patch applied.

What am I missing?

The reward for the right answer will be HDMI CEC support for omap4 (and any other TI device
with the same CEC IP).

Regards,

	Hans

diff --git a/drivers/gpu/drm/omapdrm/dss/hdmi4.c b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
index 7103c65..999b5ec 100644
--- a/drivers/gpu/drm/omapdrm/dss/hdmi4.c
+++ b/drivers/gpu/drm/omapdrm/dss/hdmi4.c
@@ -75,6 +75,14 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
 	irqstatus = hdmi_wp_get_irqstatus(wp);
 	hdmi_wp_set_irqstatus(wp, irqstatus);

+	pr_info("irqstat %08x wp_irq %08x raw %08x intr_state %08x intr1 %08x unmask1 %08x intr_ctrl %08x\n",
+		irqstatus,
+		hdmi_read_reg(hdmi.wp.base, HDMI_WP_IRQENABLE_SET),
+		hdmi_read_reg(hdmi.wp.base, HDMI_WP_IRQSTATUS_RAW),
+		hdmi_read_reg(hdmi.core.base, HDMI_CORE_SYS_INTR_STATE),
+		hdmi_read_reg(hdmi.core.base, HDMI_CORE_SYS_INTR1),
+		hdmi_read_reg(hdmi.core.base, HDMI_CORE_SYS_INTR_UNMASK1),
+		hdmi_read_reg(hdmi.core.base, HDMI_CORE_SYS_INTR_CTRL));
 	if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
 			irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
 		/*
@@ -94,6 +102,13 @@ static irqreturn_t hdmi_irq_handler(int irq, void *data)
 	} else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
 		hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
 	}
+	if (irqstatus & HDMI_IRQ_CORE) {
+		u32 intr1 = hdmi_read_reg(hdmi.core.base, HDMI_CORE_SYS_INTR1);
+
+		hdmi_write_reg(hdmi.core.base, HDMI_CORE_SYS_INTR_CTRL, 2);
+		pr_info("clear sw irq\n");
+		hdmi_write_reg(hdmi.core.base, HDMI_CORE_SYS_INTR1, intr1);
+	}

 	return IRQ_HANDLED;
 }
@@ -222,9 +237,12 @@ static int hdmi_power_on_full(struct omap_dss_device *dssdev)
 	if (r)
 		goto err_mgr_enable;

+	hdmi_write_reg(hdmi.core.base, HDMI_CORE_SYS_INTR_UNMASK1, 0x80);
 	hdmi_wp_set_irqenable(wp,
-		HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
+		HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT | HDMI_IRQ_CORE);

+	pr_info("set sw irq\n");
+	hdmi_write_reg(hdmi.core.base, HDMI_CORE_SYS_INTR_CTRL, 0xa);
 	return 0;

 err_mgr_enable: