[PATCH V3 2/4] soc/tegra: pmc: Correct type of variable for tegra_pmc_readl()

[Laxman Dewangan]

On Thursday 05 May 2016 03:19 PM, Jon Hunter wrote:
> On 04/05/16 12:39, Laxman Dewangan wrote:
>> The function tegra_pmc_readl() returns the u32 type data and hence
>> change the data type of variable where this data is stored to u32
>> type.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan at nvidia.com>
>>
>> ---
>> Changes from V1:
>> -This is new in series as per discussion on V1 series to use u32 for
>> tegra_pmc_readl.
>>
>> Changes from V2:
>> - Make unsigned long to u32 for some missed variable from V1.
>> ---
>>   drivers/soc/tegra/pmc.c | 24 ++++++++++++++----------
>>   1 file changed, 14 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c
>> index 2c3f1f9..eff9425 100644
>> --- a/drivers/soc/tegra/pmc.c
>> +++ b/drivers/soc/tegra/pmc.c
>> @@ -844,7 +844,8 @@ static void tegra_powergate_init(struct tegra_pmc *pmc)
>>   static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
>>   				 unsigned long *status, unsigned int *bit)
>>   {
>> -	unsigned long rate, value;
>> +	unsigned long rate;
>> +	u32 value;
>>   
>>   	*bit = id % 32;
>>   
>> @@ -868,17 +869,18 @@ static int tegra_io_rail_prepare(unsigned int id, unsigned long *request,
>>   	tegra_pmc_writel(DPD_SAMPLE_ENABLE, DPD_SAMPLE);
>>   
>>   	/* must be at least 200 ns, in APB (PCLK) clock cycles */
>> -	value = DIV_ROUND_UP(1000000000, rate);
>> -	value = DIV_ROUND_UP(200, value);
>> +	rate = DIV_ROUND_UP(1000000000, rate);
>> +	rate = DIV_ROUND_UP(200, rate);
>> +	value = (u32)rate;
> Although it is unlikely, I think that we should check it is less
> than U32_MAX, return an error if it is not.

rate = DIV_ROUNC_UP(200, rate) means

rate = (200 + rate -1)/rate

and can not be more than 200 in any case (if rate =1).
So no need of the error check.