DRM DMA Engine

[Jose Abreu]

Hi all,

Currently I am trying to develop a DRM driver that will use
Xilinx VDMA to transfer video data to a HDMI TX Phy and I am
facing a difficulty regarding the understanding of the DRM DMA
Engine. I looked at several sources and at the DRM core source
but the flow of creating and interfacing with the DMA controller
is still not clear to me.

At DRI web page the X server is mentioned. Does it mean that the
channel creation and handling is done by the X server? If so,
what is the DRM driver responsible to do then and what exactly
does the DRM core do? As I am using Xilinx VDMA do you foresee
any special implementation details?

Just for reference here is the description of the Xilinx VDMA:
"The Advanced eXtensible Interface Video Direct Memory Access
(AXI VDMA) core is a soft Xilinx Intellectual Property (IP) core
providing high-bandwidth direct memory access between memory and
AXI4-Stream video type target peripherals including  peripherals
which support AXI4-Stream Video Protocol." The driver is
available at "drivers/dma/xilinx/xilinx_vdma.c".

Another important point: I am using PCI Express connected to a
FPGA which has all the necessary components (Xilinx VDMA, I2S,
...) and the HDMI TX Phy.

Looking forward to you help.

Best regards,
Jose Miguel Abreu