[PATCH] drm/tegra: add tiling FB modifiers

[Daniel Vetter]

On Tue, Nov 08, 2016 at 04:50:42PM +0900, Alexandre Courbot wrote:
> Add FB modifiers to allow user-space to specify that a surface is in one
> of the two tiling formats supported by Tegra chips, and add support in
> the tegradrm driver to handle them properly. This is necessary for the
> display controller to directly display buffers generated by the GPU.
> 
> This feature is intended to replace the dedicated IOCTL enabled
> by TEGRA_STAGING and to provide a non-staging alternative to that
> solution.
> 
> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com>

Ack on the drm_fourcc.h part, I think that's the amount of detail in
comments that's reasonable. Feel free to merge through tegra trees.
-Daniel

> ---
>  drivers/gpu/drm/tegra/drm.c   |  2 ++
>  drivers/gpu/drm/tegra/fb.c    | 23 +++++++++++++++++++---
>  include/uapi/drm/drm_fourcc.h | 45 +++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 67 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm/tegra/drm.c
> index a9630c2d6cb3..36b4b30a5164 100644
> --- a/drivers/gpu/drm/tegra/drm.c
> +++ b/drivers/gpu/drm/tegra/drm.c
> @@ -161,6 +161,8 @@ static int tegra_drm_load(struct drm_device *drm, unsigned long flags)
>  	drm->mode_config.max_width = 4096;
>  	drm->mode_config.max_height = 4096;
>  
> +	drm->mode_config.allow_fb_modifiers = true;
> +
>  	drm->mode_config.funcs = &tegra_drm_mode_funcs;
>  
>  	err = tegra_drm_fb_prepare(drm);
> diff --git a/drivers/gpu/drm/tegra/fb.c b/drivers/gpu/drm/tegra/fb.c
> index e6d71fa4028e..2fded58b2ca5 100644
> --- a/drivers/gpu/drm/tegra/fb.c
> +++ b/drivers/gpu/drm/tegra/fb.c
> @@ -52,9 +52,26 @@ int tegra_fb_get_tiling(struct drm_framebuffer *framebuffer,
>  			struct tegra_bo_tiling *tiling)
>  {
>  	struct tegra_fb *fb = to_tegra_fb(framebuffer);
> -
> -	/* TODO: handle YUV formats? */
> -	*tiling = fb->planes[0]->tiling;
> +	uint64_t modifier = fb->base.modifier[0];
> +
> +	switch (fourcc_mod_tegra_mod(modifier)) {
> +	case NV_FORMAT_MOD_TEGRA_TILED:
> +		tiling->mode = TEGRA_BO_TILING_MODE_TILED;
> +		tiling->value = 0;
> +		break;
> +
> +	case NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(0):
> +		tiling->mode = TEGRA_BO_TILING_MODE_BLOCK;
> +		tiling->value = fourcc_mod_tegra_param(modifier);
> +		if (tiling->value > 5)
> +			return -EINVAL;
> +		break;
> +
> +	default:
> +		/* TODO: handle YUV formats? */
> +		*tiling = fb->planes[0]->tiling;
> +		break;
> +	}
>  
>  	return 0;
>  }
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index a5890bf44c0a..967dfab16881 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -233,6 +233,51 @@ extern "C" {
>   */
>  #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
>  
> +
> +/* NVIDIA Tegra frame buffer modifiers */
> +
> +/*
> + * Some modifiers take parameters, for example the number of vertical GOBs in
> + * a block. Reserve the lower 32 bits for parameters
> + */
> +#define __fourcc_mod_tegra_mode_shift 32
> +#define fourcc_mod_tegra_code(val, params) \
> +	fourcc_mod_code(NV, ((((__u64)val) << __fourcc_mod_tegra_mode_shift) | params))
> +#define fourcc_mod_tegra_mod(m) \
> +	(m & ~((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
> +#define fourcc_mod_tegra_param(m) \
> +	(m & ((1ULL << __fourcc_mod_tegra_mode_shift) - 1))
> +
> +/*
> + * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
> + *
> + * Pixels are arranged in simple tiles of 16 x 16 bytes.
> + */
> +#define NV_FORMAT_MOD_TEGRA_TILED fourcc_mod_tegra_code(1, 0)
> +
> +/*
> + * Tegra 16Bx2 Block Linear layout, used by TK1/TX1
> + *
> + * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
> + * vertically by a power of 2 (1 to 32 GOBs) to form a block.
> + *
> + * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
> + *
> + * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
> + * Valid values are:
> + *
> + * 0 == ONE_GOB
> + * 1 == TWO_GOBS
> + * 2 == FOUR_GOBS
> + * 3 == EIGHT_GOBS
> + * 4 == SIXTEEN_GOBS
> + * 5 == THIRTYTWO_GOBS
> + *
> + * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
> + * in full detail.
> + */
> +#define NV_FORMAT_MOD_TEGRA_16BX2_BLOCK(v) fourcc_mod_tegra_code(2, v)
> +
>  #if defined(__cplusplus)
>  }
>  #endif
> -- 
> 2.10.2
> 
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-- 
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch