[PATCH libdrm] libdrm: random typo fixes
Alex Deucher
alexdeucher at gmail.com
Mon Nov 21 19:55:46 UTC 2016
On Sun, Nov 20, 2016 at 1:25 PM, Grazvydas Ignotas <notasas at gmail.com> wrote:
> Just some trivial boring typo fixes all over the tree.
> READMEs and comments only.
>
> Signed-off-by: Grazvydas Ignotas <notasas at gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher at amd.com>
> ---
> README | 2 +-
> include/drm/README | 2 +-
> intel/intel_bufmgr_fake.c | 4 ++--
> intel/intel_bufmgr_gem.c | 6 +++---
> radeon/radeon_cs_gem.c | 10 +++++-----
> radeon/radeon_surface.c | 2 +-
> 6 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/README b/README
> index 603a1c1..7eeae38 100644
> --- a/README
> +++ b/README
> @@ -1,7 +1,7 @@
> libdrm - userspace library for drm
>
> This is libdrm, a userspace library for accessing the DRM, direct
> -rendering manager, on Linux, BSD and other operating systes that
> +rendering manager, on Linux, BSD and other operating systems that
> support the ioctl interface. The library provides wrapper functions
> for the ioctls to avoid exposing the kernel interface directly, and
> for chipsets with drm memory manager, support for tracking relocations
> diff --git a/include/drm/README b/include/drm/README
> index c3292f3..a50b02c 100644
> --- a/include/drm/README
> +++ b/include/drm/README
> @@ -89,7 +89,7 @@ Nearly all headers:
> Status: Trivial.
>
> Most UMS headers:
> - - Not using fixed size interers - compat ioctls are broken.
> + - Not using fixed size integers - compat ioctls are broken.
> Status: ?
> Promote to fixed size ints, which match the current (32bit) ones.
>
> diff --git a/intel/intel_bufmgr_fake.c b/intel/intel_bufmgr_fake.c
> index 24b3732..641df6a 100644
> --- a/intel/intel_bufmgr_fake.c
> +++ b/intel/intel_bufmgr_fake.c
> @@ -737,7 +737,7 @@ drm_intel_bufmgr_fake_wait_idle(drm_intel_bufmgr_fake *bufmgr_fake)
> /**
> * Wait for rendering to a buffer to complete.
> *
> - * It is assumed that the bathcbuffer which performed the rendering included
> + * It is assumed that the batchbuffer which performed the rendering included
> * the necessary flushing.
> */
> static void
> @@ -1200,7 +1200,7 @@ static int
> assert(!(bo_fake->flags & (BM_NO_BACKING_STORE | BM_PINNED)));
>
> /* Actually, should be able to just wait for a fence on the
> - * mmory, hich we would be tracking when we free it. Waiting
> + * memory, which we would be tracking when we free it. Waiting
> * for idle is a sufficiently large hammer for now.
> */
> drm_intel_bufmgr_fake_wait_idle(bufmgr_fake);
> diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c
> index 15c79b3..612b125 100644
> --- a/intel/intel_bufmgr_gem.c
> +++ b/intel/intel_bufmgr_gem.c
> @@ -256,7 +256,7 @@ struct _drm_intel_bo_gem {
> * Boolean of whether the GPU is definitely not accessing the buffer.
> *
> * This is only valid when reusable, since non-reusable
> - * buffers are those that have been shared wth other
> + * buffers are those that have been shared with other
> * processes, so we don't know their state.
> */
> bool idle;
> @@ -294,7 +294,7 @@ struct _drm_intel_bo_gem {
> */
> int reloc_tree_fences;
>
> - /** Flags that we may need to do the SW_FINSIH ioctl on unmap. */
> + /** Flags that we may need to do the SW_FINISH ioctl on unmap. */
> bool mapped_cpu_write;
> };
>
> @@ -1719,7 +1719,7 @@ static int drm_intel_gem_bo_unmap(drm_intel_bo *bo)
> }
>
> /* We need to unmap after every innovation as we cannot track
> - * an open vma for every bo as that will exhaasut the system
> + * an open vma for every bo as that will exhaust the system
> * limits and cause later failures.
> */
> if (--bo_gem->map_count == 0) {
> diff --git a/radeon/radeon_cs_gem.c b/radeon/radeon_cs_gem.c
> index 23f33af..f3dccb6 100644
> --- a/radeon/radeon_cs_gem.c
> +++ b/radeon/radeon_cs_gem.c
> @@ -189,7 +189,7 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
> /* check domains */
> if ((read_domain && write_domain) || (!read_domain && !write_domain)) {
> /* in one CS a bo can only be in read or write domain but not
> - * in read & write domain at the same sime
> + * in read & write domain at the same time
> */
> return -EINVAL;
> }
> @@ -242,7 +242,7 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
> }
> /* new relocation */
> if (csg->base.crelocs >= csg->nrelocs) {
> - /* allocate more memory (TODO: should use a slab allocatore maybe) */
> + /* allocate more memory (TODO: should use a slab allocator maybe) */
> uint32_t *tmp, size;
> size = ((csg->nrelocs + 1) * sizeof(struct radeon_bo*));
> tmp = (uint32_t*)realloc(csg->relocs_bo, size);
> @@ -268,7 +268,7 @@ static int cs_gem_write_reloc(struct radeon_cs_int *cs,
> reloc->flags = flags;
> csg->chunks[1].length_dw += RELOC_SIZE;
> radeon_bo_ref(bo);
> - /* bo might be referenced from another context so have to use atomic opertions */
> + /* bo might be referenced from another context so have to use atomic operations */
> atomic_add((atomic_t *)radeon_gem_get_reloc_in_cs(bo), cs->id);
> cs->relocs_total_size += boi->size;
> radeon_cs_write_dword((struct radeon_cs *)cs, 0xc0001000);
> @@ -449,7 +449,7 @@ static int cs_gem_emit(struct radeon_cs_int *cs)
> &csg->cs, sizeof(struct drm_radeon_cs));
> for (i = 0; i < csg->base.crelocs; i++) {
> csg->relocs_bo[i]->space_accounted = 0;
> - /* bo might be referenced from another context so have to use atomic opertions */
> + /* bo might be referenced from another context so have to use atomic operations */
> atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id);
> radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
> csg->relocs_bo[i] = NULL;
> @@ -481,7 +481,7 @@ static int cs_gem_erase(struct radeon_cs_int *cs)
> if (csg->relocs_bo) {
> for (i = 0; i < csg->base.crelocs; i++) {
> if (csg->relocs_bo[i]) {
> - /* bo might be referenced from another context so have to use atomic opertions */
> + /* bo might be referenced from another context so have to use atomic operations */
> atomic_dec((atomic_t *)radeon_gem_get_reloc_in_cs((struct radeon_bo*)csg->relocs_bo[i]), cs->id);
> radeon_bo_unref((struct radeon_bo *)csg->relocs_bo[i]);
> csg->relocs_bo[i] = NULL;
> diff --git a/radeon/radeon_surface.c b/radeon/radeon_surface.c
> index 16a8b00..965be24 100644
> --- a/radeon/radeon_surface.c
> +++ b/radeon/radeon_surface.c
> @@ -981,7 +981,7 @@ static int eg_surface_best(struct radeon_surface_manager *surf_man,
> /* bankw or bankh greater than 1 increase alignment requirement, not
> * sure if it's worth using smaller bankw & bankh to stick with 2D
> * tiling on small surface rather than falling back to 1D tiling.
> - * Use recommanded value based on tile size for now.
> + * Use recommended value based on tile size for now.
> *
> * fmask buffer has different optimal value figure them out once we
> * use it.
> --
> 2.7.4
>
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