[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #7 from Arek Ruśniak <arek.rusi at gmail.com> ---
Alex I use something like that:
watch -n 1 -c "cat /sys/kernel/debug/dri/0/amdgpu_pm_info"
combined with 
vblank_mode=0 glxgears
it should set mclk on fire IIRC, but it was still 300MHz, bisecting gives me:
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=ddfe1db18752b08d88d81cb7b661e1f982fc5d04

but when I've tested (in the bisecting proces) commit [1] I saw that mclk i set
always on 2000MHz... and this is first commit (I checked +/- 1) when is set on
HIGH no matter what.

So yes, this are two issues in one I believe because revert
1b7eab1f8346ab3b8e4fc54882306340a84497a8 fixes them all.

-- 
You are receiving this mail because:
You are the assignee for the bug.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://lists.freedesktop.org/archives/dri-devel/attachments/20161122/14a7a8ee/attachment.html>