[Bug 98821] [amdgpu][bisected][polaris] "drm/amdgpu: refine uvd 6.0 clock gate feature" sets MCLK on highest state

[bugzilla-daemon at freedesktop.org]

https://bugs.freedesktop.org/show_bug.cgi?id=98821

--- Comment #15 from Arek Ruśniak <arek.rusi at gmail.com> ---
still broken with
https://cgit.freedesktop.org/~agd5f/linux/commit/?h=drm-next-4.10-wip&id=7ee83d80bb305cce211d1bf1745a49af4d749f47

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