[bug report] drm/amd/powerplay: implement fw related smu interface for iceland.

[Dan Carpenter]

Hello Rex Zhu,

The patch 18aafc59b106: "drm/amd/powerplay: implement fw related smu
interface for iceland." from Aug 23, 2016, leads to the following
static checker warning:

	drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/iceland_smc.c:2462 iceland_set_mc_special_registers()
	error: buffer overflow 'table->mc_reg_address' 16 <= 16

drivers/gpu/drm/amd/amdgpu/../powerplay/smumgr/iceland_smc.c
  2441                          j++;
  2442                          PP_ASSERT_WITH_CODE((j < SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),
                                                     ^^^^^^^^^^
Note the < here.

  2443                                  "Invalid VramInfo table.", return -EINVAL);
  2444  
  2445                          temp_reg = cgs_read_register(hwmgr->device, mmMC_PMG_CMD_MRS);
  2446                          table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
  2447                          table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
  2448                          for (k = 0; k < table->num_entries; k++) {
  2449                                  table->mc_reg_table_entry[k].mc_data[j] =
  2450                                          (temp_reg & 0xffff0000) |
  2451                                          (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
  2452  
  2453                                  if (!data->is_memory_gddr5) {
  2454                                          table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
  2455                                  }
  2456                          }
  2457                          j++;
  2458                          PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),


This should be < as well.

  2459                                  "Invalid VramInfo table.", return -EINVAL);
  2460  
  2461                          if (!data->is_memory_gddr5) {
  2462                                  table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
  2463                                  table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
  2464                                  for (k = 0; k < table->num_entries; k++) {
  2465                                          table->mc_reg_table_entry[k].mc_data[j] =
  2466                                                  (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
  2467                                  }
  2468                                  j++;
  2469                                  PP_ASSERT_WITH_CODE((j <= SMU71_DISCRETE_MC_REGISTER_ARRAY_SIZE),

But I don't know about this one.

  2470                                          "Invalid VramInfo table.", return -EINVAL);
  2471                          }
  2472  
  2473                          break;
  2474  
  2475                  case mmMC_SEQ_RESERVE_M:


regards,
dan carpenter