[PATCH] drm/fsl-dcu: Add gamma set for crtc

[Stefan Agner]

On 2016-09-03 03:49, Mark Brown wrote:
> On Fri, Sep 02, 2016 at 02:22:46PM -0700, Stefan Agner wrote:
>> I guess the problem is that regmap_write does byte swapping because
>> ls1021a.dtsi defines the whole DCU register space to be big-endian. So
>> you end up doing byte swapping twice.
> 
>> If the gamma area is really little-endian, then DCU on LS1021a seems to
>> be quite a mess... :-(
> 
> Let's figure out what the hardware does first, espcially given that it's
> this chip where we seem to be seeing a lot of confusion about endianness
> issues.
> 

According to Meng it is an errata for that whole area on that particular
SoC (LS1021a)...

Note that on Vybrid (the SoC I have on the table here) the whole DCU IP
is little-endian, including the gamma area.

>> @Mark, what do you think? Do we have a (better) solution for such cases?
> 
> Is this area of the register map perhaps supposed to be accessed as a
> byte stream?

I don't think so, the Vybrid RM calls the area a table:

The table is arranged as three separate memory blocks within the DCU4
memory map; one for each of the three color components. Each memory
block has one entry for every possible 8-bit value and the entries are
stored at 32-bit aligned addresses. This means that the upper 24 bits
are not used while reading/writing the gamma memories. See Figure 16-22
for details of the memory arrangement.

So, afaik, we deal with 3x 256 32-bit register which happen to be a
different endianness on one SoC implementing the DCU IP...

--
Stefan