[PATCH v2] drm/sti: remove stih415-416 platform support

Benjamin Gaignard benjamin.gaignard at linaro.org
Tue Sep 20 12:42:23 UTC 2016


Acked-by: Benjamin Gaignard <benjamin.gaignard at linaro.org>

2016-09-20 11:25 GMT+02:00 Vincent Abriou <vincent.abriou at st.com>:
> stih415 and stih416 platform are obsolete and no more supported.
> Only stih407 and stih410 platform are maintained.
>
> Signed-off-by: Vincent Abriou <vincent.abriou at st.com>
> ---
>  drivers/gpu/drm/sti/Kconfig                |   6 +-
>  drivers/gpu/drm/sti/Makefile               |   1 -
>  drivers/gpu/drm/sti/sti_compositor.c       |  19 --
>  drivers/gpu/drm/sti/sti_hda.c              |  39 +---
>  drivers/gpu/drm/sti/sti_hdmi.c             |  20 --
>  drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c | 336 -----------------------------
>  drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h |  14 --
>  drivers/gpu/drm/sti/sti_mixer.c            |  19 --
>  drivers/gpu/drm/sti/sti_tvout.c            |  40 +---
>  9 files changed, 14 insertions(+), 480 deletions(-)
>  delete mode 100644 drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c
>  delete mode 100644 drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h
>
> diff --git a/drivers/gpu/drm/sti/Kconfig b/drivers/gpu/drm/sti/Kconfig
> index 494ab25..acd7286 100644
> --- a/drivers/gpu/drm/sti/Kconfig
> +++ b/drivers/gpu/drm/sti/Kconfig
> @@ -1,6 +1,6 @@
>  config DRM_STI
> -       tristate "DRM Support for STMicroelectronics SoC stiH41x Series"
> -       depends on DRM && (SOC_STIH415 || SOC_STIH416 || ARCH_MULTIPLATFORM)
> +       tristate "DRM Support for STMicroelectronics SoC stiH4xx Series"
> +       depends on DRM && (ARCH_STI || ARCH_MULTIPLATFORM)
>         select RESET_CONTROLLER
>         select DRM_KMS_HELPER
>         select DRM_GEM_CMA_HELPER
> @@ -9,4 +9,4 @@ config DRM_STI
>         select FW_LOADER
>         select SND_SOC_HDMI_CODEC if SND_SOC
>         help
> -         Choose this option to enable DRM on STM stiH41x chipset
> +         Choose this option to enable DRM on STM stiH4xx chipset
> diff --git a/drivers/gpu/drm/sti/Makefile b/drivers/gpu/drm/sti/Makefile
> index b805762..d20f7c0 100644
> --- a/drivers/gpu/drm/sti/Makefile
> +++ b/drivers/gpu/drm/sti/Makefile
> @@ -9,7 +9,6 @@ sti-drm-y := \
>         sti_crtc.o \
>         sti_plane.o \
>         sti_hdmi.o \
> -       sti_hdmi_tx3g0c55phy.o \
>         sti_hdmi_tx3g4c28phy.o \
>         sti_dvo.o \
>         sti_awg_utils.o \
> diff --git a/drivers/gpu/drm/sti/sti_compositor.c b/drivers/gpu/drm/sti/sti_compositor.c
> index a6f391b..f62041f 100644
> --- a/drivers/gpu/drm/sti/sti_compositor.c
> +++ b/drivers/gpu/drm/sti/sti_compositor.c
> @@ -39,22 +39,6 @@ static const struct sti_compositor_data stih407_compositor_data = {
>         },
>  };
>
> -/*
> - * stiH416 compositor properties
> - * Note:
> - * on stih416 MIXER_AUX has a different base address from MIXER_MAIN
> - * Moreover, GDPx is different for Main and Aux Mixer. So this subdev map does
> - * not fit for stiH416 if we want to enable the MIXER_AUX.
> - */
> -static const struct sti_compositor_data stih416_compositor_data = {
> -       .nb_subdev = 3,
> -       .subdev_desc = {
> -                       {STI_GPD_SUBDEV, (int)STI_GDP_0, 0x100},
> -                       {STI_GPD_SUBDEV, (int)STI_GDP_1, 0x200},
> -                       {STI_MIXER_MAIN_SUBDEV, STI_MIXER_MAIN, 0xC00}
> -       },
> -};
> -
>  int sti_compositor_debugfs_init(struct sti_compositor *compo,
>                                 struct drm_minor *minor)
>  {
> @@ -179,9 +163,6 @@ static const struct component_ops sti_compositor_ops = {
>
>  static const struct of_device_id compositor_of_match[] = {
>         {
> -               .compatible = "st,stih416-compositor",
> -               .data = &stih416_compositor_data,
> -       }, {
>                 .compatible = "st,stih407-compositor",
>                 .data = &stih407_compositor_data,
>         }, {
> diff --git a/drivers/gpu/drm/sti/sti_hda.c b/drivers/gpu/drm/sti/sti_hda.c
> index a225c4d..e7c243f 100644
> --- a/drivers/gpu/drm/sti/sti_hda.c
> +++ b/drivers/gpu/drm/sti/sti_hda.c
> @@ -62,14 +62,8 @@
>  #define SCALE_CTRL_CR_DFLT              0x00DB0249
>
>  /* Video DACs control */
> -#define VIDEO_DACS_CONTROL_MASK         0x0FFF
> -#define VIDEO_DACS_CONTROL_SYSCFG2535   0x085C /* for stih416 */
> -#define DAC_CFG_HD_OFF_SHIFT            5
> -#define DAC_CFG_HD_OFF_MASK             (0x7 << DAC_CFG_HD_OFF_SHIFT)
> -#define VIDEO_DACS_CONTROL_SYSCFG5072   0x0120 /* for stih407 */
>  #define DAC_CFG_HD_HZUVW_OFF_MASK       BIT(1)
>
> -
>  /* Upsampler values for the alternative 2X Filter */
>  #define SAMPLER_COEF_NB                 8
>  #define HDA_ANA_SRC_Y_CFG_ALT_2X        0x01130000
> @@ -300,28 +294,14 @@ static bool hda_get_mode_idx(struct drm_display_mode mode, int *idx)
>   */
>  static void hda_enable_hd_dacs(struct sti_hda *hda, bool enable)
>  {
> -       u32 mask;
> -
>         if (hda->video_dacs_ctrl) {
>                 u32 val;
>
> -               switch ((u32)hda->video_dacs_ctrl & VIDEO_DACS_CONTROL_MASK) {
> -               case VIDEO_DACS_CONTROL_SYSCFG2535:
> -                       mask = DAC_CFG_HD_OFF_MASK;
> -                       break;
> -               case VIDEO_DACS_CONTROL_SYSCFG5072:
> -                       mask = DAC_CFG_HD_HZUVW_OFF_MASK;
> -                       break;
> -               default:
> -                       DRM_INFO("Video DACS control register not supported\n");
> -                       return;
> -               }
> -
>                 val = readl(hda->video_dacs_ctrl);
>                 if (enable)
> -                       val &= ~mask;
> +                       val &= ~DAC_CFG_HD_HZUVW_OFF_MASK;
>                 else
> -                       val |= mask;
> +                       val |= DAC_CFG_HD_HZUVW_OFF_MASK;
>
>                 writel(val, hda->video_dacs_ctrl);
>         }
> @@ -352,24 +332,11 @@ static void hda_dbg_awg_microcode(struct seq_file *s, void __iomem *reg)
>  static void hda_dbg_video_dacs_ctrl(struct seq_file *s, void __iomem *reg)
>  {
>         u32 val = readl(reg);
> -       u32 mask;
> -
> -       switch ((u32)reg & VIDEO_DACS_CONTROL_MASK) {
> -       case VIDEO_DACS_CONTROL_SYSCFG2535:
> -               mask = DAC_CFG_HD_OFF_MASK;
> -               break;
> -       case VIDEO_DACS_CONTROL_SYSCFG5072:
> -               mask = DAC_CFG_HD_HZUVW_OFF_MASK;
> -               break;
> -       default:
> -               DRM_DEBUG_DRIVER("Warning: DACS ctrl register not supported\n");
> -               return;
> -       }
>
>         seq_puts(s, "\n");
>         seq_printf(s, "\n  %-25s 0x%08X", "VIDEO_DACS_CONTROL", val);
>         seq_puts(s, "\tHD DACs ");
> -       seq_puts(s, val & mask ? "disabled" : "enabled");
> +       seq_puts(s, val & DAC_CFG_HD_HZUVW_OFF_MASK ? "disabled" : "enabled");
>  }
>
>  static int hda_dbg_show(struct seq_file *s, void *data)
> diff --git a/drivers/gpu/drm/sti/sti_hdmi.c b/drivers/gpu/drm/sti/sti_hdmi.c
> index 1f9e7b4..376b076 100644
> --- a/drivers/gpu/drm/sti/sti_hdmi.c
> +++ b/drivers/gpu/drm/sti/sti_hdmi.c
> @@ -22,7 +22,6 @@
>
>  #include "sti_hdmi.h"
>  #include "sti_hdmi_tx3g4c28phy.h"
> -#include "sti_hdmi_tx3g0c55phy.h"
>  #include "sti_vtg.h"
>
>  #define HDMI_CFG                        0x0000
> @@ -1374,9 +1373,6 @@ static const struct component_ops sti_hdmi_ops = {
>
>  static const struct of_device_id hdmi_of_match[] = {
>         {
> -               .compatible = "st,stih416-hdmi",
> -               .data = &tx3g0c55phy_ops,
> -       }, {
>                 .compatible = "st,stih407-hdmi",
>                 .data = &tx3g4c28phy_ops,
>         }, {
> @@ -1423,22 +1419,6 @@ static int sti_hdmi_probe(struct platform_device *pdev)
>                 goto release_adapter;
>         }
>
> -       if (of_device_is_compatible(np, "st,stih416-hdmi")) {
> -               res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
> -                                                  "syscfg");
> -               if (!res) {
> -                       DRM_ERROR("Invalid syscfg resource\n");
> -                       ret = -ENOMEM;
> -                       goto release_adapter;
> -               }
> -               hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
> -                                                   resource_size(res));
> -               if (!hdmi->syscfg) {
> -                       ret = -ENOMEM;
> -                       goto release_adapter;
> -               }
> -       }
> -
>         hdmi->phy_ops = (struct hdmi_phy_ops *)
>                 of_match_node(hdmi_of_match, np)->data;
>
> diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c b/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c
> deleted file mode 100644
> index 49ae8e4..0000000
> --- a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.c
> +++ /dev/null
> @@ -1,336 +0,0 @@
> -/*
> - * Copyright (C) STMicroelectronics SA 2014
> - * Author: Vincent Abriou <vincent.abriou at st.com> for STMicroelectronics.
> - * License terms:  GNU General Public License (GPL), version 2
> - */
> -
> -#include "sti_hdmi_tx3g0c55phy.h"
> -
> -#define HDMI_SRZ_PLL_CFG                0x0504
> -#define HDMI_SRZ_TAP_1                  0x0508
> -#define HDMI_SRZ_TAP_2                  0x050C
> -#define HDMI_SRZ_TAP_3                  0x0510
> -#define HDMI_SRZ_CTRL                   0x0514
> -
> -#define HDMI_SRZ_PLL_CFG_POWER_DOWN     BIT(0)
> -#define HDMI_SRZ_PLL_CFG_VCOR_SHIFT     1
> -#define HDMI_SRZ_PLL_CFG_VCOR_425MHZ    0
> -#define HDMI_SRZ_PLL_CFG_VCOR_850MHZ    1
> -#define HDMI_SRZ_PLL_CFG_VCOR_1700MHZ   2
> -#define HDMI_SRZ_PLL_CFG_VCOR_3000MHZ   3
> -#define HDMI_SRZ_PLL_CFG_VCOR_MASK      3
> -#define HDMI_SRZ_PLL_CFG_VCOR(x)        (x << HDMI_SRZ_PLL_CFG_VCOR_SHIFT)
> -#define HDMI_SRZ_PLL_CFG_NDIV_SHIFT     8
> -#define HDMI_SRZ_PLL_CFG_NDIV_MASK      (0x1F << HDMI_SRZ_PLL_CFG_NDIV_SHIFT)
> -#define HDMI_SRZ_PLL_CFG_MODE_SHIFT     16
> -#define HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ  0x1
> -#define HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ  0x4
> -#define HDMI_SRZ_PLL_CFG_MODE_27_MHZ    0x5
> -#define HDMI_SRZ_PLL_CFG_MODE_33_75_MHZ 0x6
> -#define HDMI_SRZ_PLL_CFG_MODE_40_5_MHZ  0x7
> -#define HDMI_SRZ_PLL_CFG_MODE_54_MHZ    0x8
> -#define HDMI_SRZ_PLL_CFG_MODE_67_5_MHZ  0x9
> -#define HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ 0xA
> -#define HDMI_SRZ_PLL_CFG_MODE_81_MHZ    0xB
> -#define HDMI_SRZ_PLL_CFG_MODE_82_5_MHZ  0xC
> -#define HDMI_SRZ_PLL_CFG_MODE_108_MHZ   0xD
> -#define HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ 0xE
> -#define HDMI_SRZ_PLL_CFG_MODE_165_MHZ   0xF
> -#define HDMI_SRZ_PLL_CFG_MODE_MASK      0xF
> -#define HDMI_SRZ_PLL_CFG_MODE(x)        (x << HDMI_SRZ_PLL_CFG_MODE_SHIFT)
> -
> -#define HDMI_SRZ_CTRL_POWER_DOWN        (1 << 0)
> -#define HDMI_SRZ_CTRL_EXTERNAL_DATA_EN  (1 << 1)
> -
> -/* sysconf registers */
> -#define HDMI_REJECTION_PLL_CONFIGURATION 0x0858        /* SYSTEM_CONFIG2534 */
> -#define HDMI_REJECTION_PLL_STATUS        0x0948        /* SYSTEM_CONFIG2594 */
> -
> -#define REJECTION_PLL_HDMI_ENABLE_SHIFT 0
> -#define REJECTION_PLL_HDMI_ENABLE_MASK  (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT)
> -#define REJECTION_PLL_HDMI_PDIV_SHIFT   24
> -#define REJECTION_PLL_HDMI_PDIV_MASK    (0x7 << REJECTION_PLL_HDMI_PDIV_SHIFT)
> -#define REJECTION_PLL_HDMI_NDIV_SHIFT   16
> -#define REJECTION_PLL_HDMI_NDIV_MASK    (0xFF << REJECTION_PLL_HDMI_NDIV_SHIFT)
> -#define REJECTION_PLL_HDMI_MDIV_SHIFT   8
> -#define REJECTION_PLL_HDMI_MDIV_MASK    (0xFF << REJECTION_PLL_HDMI_MDIV_SHIFT)
> -
> -#define REJECTION_PLL_HDMI_REJ_PLL_LOCK BIT(0)
> -
> -#define HDMI_TIMEOUT_PLL_LOCK  50   /*milliseconds */
> -
> -/**
> - * pll mode structure
> - *
> - * A pointer to an array of these structures is passed to a TMDS (HDMI) output
> - * via the control interface to provide board and SoC specific
> - * configurations of the HDMI PHY. Each entry in the array specifies a hardware
> - * specific configuration for a given TMDS clock frequency range. The array
> - * should be terminated with an entry that has all fields set to zero.
> - *
> - * @min: Lower bound of TMDS clock frequency this entry applies to
> - * @max: Upper bound of TMDS clock frequency this entry applies to
> - * @mode: SoC specific register configuration
> - */
> -struct pllmode {
> -       u32 min;
> -       u32 max;
> -       u32 mode;
> -};
> -
> -#define NB_PLL_MODE 7
> -static struct pllmode pllmodes[NB_PLL_MODE] = {
> -       {13500000, 13513500, HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ},
> -       {25174800, 25200000, HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ},
> -       {27000000, 27027000, HDMI_SRZ_PLL_CFG_MODE_27_MHZ},
> -       {54000000, 54054000, HDMI_SRZ_PLL_CFG_MODE_54_MHZ},
> -       {72000000, 74250000, HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ},
> -       {108000000, 108108000, HDMI_SRZ_PLL_CFG_MODE_108_MHZ},
> -       {148351648, 297000000, HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ}
> -};
> -
> -#define NB_HDMI_PHY_CONFIG 5
> -static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = {
> -       {0, 40000000, {0x00101010, 0x00101010, 0x00101010, 0x02} },
> -       {40000000, 140000000, {0x00111111, 0x00111111, 0x00111111, 0x02} },
> -       {140000000, 160000000, {0x00131313, 0x00101010, 0x00101010, 0x02} },
> -       {160000000, 250000000, {0x00131313, 0x00111111, 0x00111111, 0x03FE} },
> -       {250000000, 300000000, {0x00151515, 0x00101010, 0x00101010, 0x03FE} },
> -};
> -
> -#define PLL_CHANGE_DELAY       1 /* ms */
> -
> -/**
> - * Disable the pll rejection
> - *
> - * @hdmi: pointer on the hdmi internal structure
> - *
> - * return true if the pll has been disabled
> - */
> -static bool disable_pll_rejection(struct sti_hdmi *hdmi)
> -{
> -       u32 val;
> -
> -       DRM_DEBUG_DRIVER("\n");
> -
> -       val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
> -       val &= ~REJECTION_PLL_HDMI_ENABLE_MASK;
> -       writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
> -
> -       msleep(PLL_CHANGE_DELAY);
> -       val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
> -
> -       return !(val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
> -}
> -
> -/**
> - * Enable the old BCH/rejection PLL is now reused to provide the CLKPXPLL
> - * clock input to the new PHY PLL that generates the serializer clock
> - * (TMDS*10) and the TMDS clock which is now fed back into the HDMI
> - * formatter instead of the TMDS clock line from ClockGenB.
> - *
> - * @hdmi: pointer on the hdmi internal structure
> - *
> - * return true if pll has been correctly set
> - */
> -static bool enable_pll_rejection(struct sti_hdmi *hdmi)
> -{
> -       unsigned int inputclock;
> -       u32 mdiv, ndiv, pdiv, val;
> -
> -       DRM_DEBUG_DRIVER("\n");
> -
> -       if (!disable_pll_rejection(hdmi))
> -               return false;
> -
> -       inputclock = hdmi->mode.clock * 1000;
> -
> -       DRM_DEBUG_DRIVER("hdmi rejection pll input clock = %dHz\n", inputclock);
> -
> -
> -       /* Power up the HDMI rejection PLL
> -        * Note: On this SoC (stiH416) we are forced to have the input clock
> -        * be equal to the HDMI pixel clock.
> -        *
> -        * The values here have been suggested by validation however they are
> -        * still provisional and subject to change.
> -        *
> -        * PLLout = (Fin*Mdiv) / ((2 * Ndiv) / 2^Pdiv)
> -        */
> -       if (inputclock < 50000000) {
> -               /*
> -                * For slower clocks we need to multiply more to keep the
> -                * internal VCO frequency within the physical specification
> -                * of the PLL.
> -                */
> -               pdiv = 4;
> -               ndiv = 240;
> -               mdiv = 30;
> -       } else {
> -               pdiv = 2;
> -               ndiv = 60;
> -               mdiv = 30;
> -       }
> -
> -       val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
> -
> -       val &= ~(REJECTION_PLL_HDMI_PDIV_MASK |
> -               REJECTION_PLL_HDMI_NDIV_MASK |
> -               REJECTION_PLL_HDMI_MDIV_MASK |
> -               REJECTION_PLL_HDMI_ENABLE_MASK);
> -
> -       val |=  (pdiv << REJECTION_PLL_HDMI_PDIV_SHIFT) |
> -               (ndiv << REJECTION_PLL_HDMI_NDIV_SHIFT) |
> -               (mdiv << REJECTION_PLL_HDMI_MDIV_SHIFT) |
> -               (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT);
> -
> -       writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
> -
> -       msleep(PLL_CHANGE_DELAY);
> -       val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
> -
> -       return (val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
> -}
> -
> -/**
> - * Start hdmi phy macro cell tx3g0c55
> - *
> - * @hdmi: pointer on the hdmi internal structure
> - *
> - * Return false if an error occur
> - */
> -static bool sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi)
> -{
> -       u32 ckpxpll = hdmi->mode.clock * 1000;
> -       u32 val, tmdsck, freqvco, pllctrl = 0;
> -       unsigned int i;
> -
> -       if (!enable_pll_rejection(hdmi))
> -               return false;
> -
> -       DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll);
> -
> -       /* Assuming no pixel repetition and 24bits color */
> -       tmdsck = ckpxpll;
> -       pllctrl = 2 << HDMI_SRZ_PLL_CFG_NDIV_SHIFT;
> -
> -       /*
> -        * Setup the PLL mode parameter based on the ckpxpll. If we haven't got
> -        * a clock frequency supported by one of the specific PLL modes then we
> -        * will end up using the generic mode (0) which only supports a 10x
> -        * multiplier, hence only 24bit color.
> -        */
> -       for (i = 0; i < NB_PLL_MODE; i++) {
> -               if (ckpxpll >= pllmodes[i].min && ckpxpll <= pllmodes[i].max)
> -                       pllctrl |= HDMI_SRZ_PLL_CFG_MODE(pllmodes[i].mode);
> -       }
> -
> -       freqvco = tmdsck * 10;
> -       if (freqvco <= 425000000UL)
> -               pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_425MHZ);
> -       else if (freqvco <= 850000000UL)
> -               pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_850MHZ);
> -       else if (freqvco <= 1700000000UL)
> -               pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_1700MHZ);
> -       else if (freqvco <= 2970000000UL)
> -               pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_3000MHZ);
> -       else {
> -               DRM_ERROR("PHY serializer clock out of range\n");
> -               goto err;
> -       }
> -
> -       /*
> -        * Configure and power up the PHY PLL
> -        */
> -       hdmi->event_received = false;
> -       DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl);
> -       hdmi_write(hdmi, pllctrl, HDMI_SRZ_PLL_CFG);
> -
> -       /* wait PLL interrupt */
> -       wait_event_interruptible_timeout(hdmi->wait_event,
> -                                        hdmi->event_received == true,
> -                                        msecs_to_jiffies
> -                                        (HDMI_TIMEOUT_PLL_LOCK));
> -
> -       if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) {
> -               DRM_ERROR("hdmi phy pll not locked\n");
> -               goto err;
> -       }
> -
> -       DRM_DEBUG_DRIVER("got PHY PLL Lock\n");
> -
> -       /*
> -        * To configure the source termination and pre-emphasis appropriately
> -        * for different high speed TMDS clock frequencies a phy configuration
> -        * table must be provided, tailored to the SoC and board combination.
> -        */
> -       for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) {
> -               if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
> -                   (hdmiphy_config[i].max_tmds_freq >= tmdsck)) {
> -                       val = hdmiphy_config[i].config[0];
> -                       hdmi_write(hdmi, val, HDMI_SRZ_TAP_1);
> -                       val = hdmiphy_config[i].config[1];
> -                       hdmi_write(hdmi, val, HDMI_SRZ_TAP_2);
> -                       val = hdmiphy_config[i].config[2];
> -                       hdmi_write(hdmi, val, HDMI_SRZ_TAP_3);
> -                       val = hdmiphy_config[i].config[3];
> -                       val |= HDMI_SRZ_CTRL_EXTERNAL_DATA_EN;
> -                       val &= ~HDMI_SRZ_CTRL_POWER_DOWN;
> -                       hdmi_write(hdmi, val, HDMI_SRZ_CTRL);
> -
> -                       DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x 0x%x\n",
> -                                        hdmiphy_config[i].config[0],
> -                                        hdmiphy_config[i].config[1],
> -                                        hdmiphy_config[i].config[2],
> -                                        hdmiphy_config[i].config[3]);
> -                       return true;
> -               }
> -       }
> -
> -       /*
> -        * Default, power up the serializer with no pre-emphasis or source
> -        * termination.
> -        */
> -       hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_1);
> -       hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_2);
> -       hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_3);
> -       hdmi_write(hdmi, HDMI_SRZ_CTRL_EXTERNAL_DATA_EN, HDMI_SRZ_CTRL);
> -
> -       return true;
> -
> -err:
> -       disable_pll_rejection(hdmi);
> -
> -       return false;
> -}
> -
> -/**
> - * Stop hdmi phy macro cell tx3g0c55
> - *
> - * @hdmi: pointer on the hdmi internal structure
> - */
> -static void sti_hdmi_tx3g0c55phy_stop(struct sti_hdmi *hdmi)
> -{
> -       DRM_DEBUG_DRIVER("\n");
> -
> -       hdmi->event_received = false;
> -
> -       hdmi_write(hdmi, HDMI_SRZ_CTRL_POWER_DOWN, HDMI_SRZ_CTRL);
> -       hdmi_write(hdmi, HDMI_SRZ_PLL_CFG_POWER_DOWN, HDMI_SRZ_PLL_CFG);
> -
> -       /* wait PLL interrupt */
> -       wait_event_interruptible_timeout(hdmi->wait_event,
> -                                        hdmi->event_received == true,
> -                                        msecs_to_jiffies
> -                                        (HDMI_TIMEOUT_PLL_LOCK));
> -
> -       if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)
> -               DRM_ERROR("hdmi phy pll not well disabled\n");
> -
> -       disable_pll_rejection(hdmi);
> -}
> -
> -struct hdmi_phy_ops tx3g0c55phy_ops = {
> -       .start = sti_hdmi_tx3g0c55phy_start,
> -       .stop = sti_hdmi_tx3g0c55phy_stop,
> -};
> diff --git a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h b/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h
> deleted file mode 100644
> index 068237b..0000000
> --- a/drivers/gpu/drm/sti/sti_hdmi_tx3g0c55phy.h
> +++ /dev/null
> @@ -1,14 +0,0 @@
> -/*
> - * Copyright (C) STMicroelectronics SA 2014
> - * Author: Benjamin Gaignard <benjamin.gaignard at st.com> for STMicroelectronics.
> - * License terms:  GNU General Public License (GPL), version 2
> - */
> -
> -#ifndef _STI_HDMI_TX3G0C55PHY_H_
> -#define _STI_HDMI_TX3G0C55PHY_H_
> -
> -#include "sti_hdmi.h"
> -
> -extern struct hdmi_phy_ops tx3g0c55phy_ops;
> -
> -#endif
> diff --git a/drivers/gpu/drm/sti/sti_mixer.c b/drivers/gpu/drm/sti/sti_mixer.c
> index b78cec5..4ddc58f 100644
> --- a/drivers/gpu/drm/sti/sti_mixer.c
> +++ b/drivers/gpu/drm/sti/sti_mixer.c
> @@ -16,12 +16,6 @@ static unsigned int bkg_color = 0x000000;
>  MODULE_PARM_DESC(bkgcolor, "Value of the background color 0xRRGGBB");
>  module_param_named(bkgcolor, bkg_color, int, 0644);
>
> -/* Identity: G=Y , B=Cb , R=Cr */
> -static const u32 mixerColorSpaceMatIdentity[] = {
> -       0x10000000, 0x00000000, 0x10000000, 0x00001000,
> -       0x00000000, 0x00000000, 0x00000000, 0x00000000
> -};
> -
>  /* regs offset */
>  #define GAM_MIXER_CTL      0x00
>  #define GAM_MIXER_BKC      0x04
> @@ -358,22 +352,12 @@ int sti_mixer_set_plane_status(struct sti_mixer *mixer,
>         return 0;
>  }
>
> -static void sti_mixer_set_matrix(struct sti_mixer *mixer)
> -{
> -       unsigned int i;
> -
> -       for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
> -               sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
> -                                   mixerColorSpaceMatIdentity[i]);
> -}
> -
>  struct sti_mixer *sti_mixer_create(struct device *dev,
>                                    struct drm_device *drm_dev,
>                                    int id,
>                                    void __iomem *baseaddr)
>  {
>         struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
> -       struct device_node *np = dev->of_node;
>
>         dev_dbg(dev, "%s\n", __func__);
>         if (!mixer) {
> @@ -384,9 +368,6 @@ struct sti_mixer *sti_mixer_create(struct device *dev,
>         mixer->dev = dev;
>         mixer->id = id;
>
> -       if (of_device_is_compatible(np, "st,stih416-compositor"))
> -               sti_mixer_set_matrix(mixer);
> -
>         DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
>                          sti_mixer_to_str(mixer), mixer->regs);
>
> diff --git a/drivers/gpu/drm/sti/sti_tvout.c b/drivers/gpu/drm/sti/sti_tvout.c
> index cc07e06..ad46d35 100644
> --- a/drivers/gpu/drm/sti/sti_tvout.c
> +++ b/drivers/gpu/drm/sti/sti_tvout.c
> @@ -210,13 +210,11 @@ static void tvout_vip_set_rnd(struct sti_tvout *tvout, int reg, u32 rnd)
>   * @tvout: tvout structure
>   * @reg: register to set
>   * @main_path: main or auxiliary path
> - * @sel_input_logic_inverted: need to invert the logic
>   * @sel_input: selected_input (main/aux + conv)
>   */
>  static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
>                                     int reg,
>                                     bool main_path,
> -                                   bool sel_input_logic_inverted,
>                                     enum sti_tvout_video_out_type video_out)
>  {
>         u32 sel_input;
> @@ -237,8 +235,7 @@ static void tvout_vip_set_sel_input(struct sti_tvout *tvout,
>         }
>
>         /* on stih407 chip the sel_input bypass mode logic is inverted */
> -       if (sel_input_logic_inverted)
> -               sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
> +       sel_input = sel_input ^ TVO_VIP_SEL_INPUT_BYPASS_MASK;
>
>         val &= ~TVO_VIP_SEL_INPUT_MASK;
>         val |= sel_input;
> @@ -296,8 +293,6 @@ static void tvout_preformatter_set_matrix(struct sti_tvout *tvout,
>   */
>  static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
>  {
> -       struct device_node *node = tvout->dev->of_node;
> -       bool sel_input_logic_inverted = false;
>         u32 tvo_in_vid_format;
>         int val, tmp;
>
> @@ -335,16 +330,11 @@ static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
>         /* Set round mode (rounded to 8-bit per component) */
>         tvout_vip_set_rnd(tvout, TVO_VIP_DVO, TVO_VIP_RND_8BIT_ROUNDED);
>
> -       if (of_device_is_compatible(node, "st,stih407-tvout")) {
> -               /* Set input video format */
> -               tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
> -                                        TVO_IN_FMT_SIGNED);
> -               sel_input_logic_inverted = true;
> -       }
> +       /* Set input video format */
> +       tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
>
>         /* Input selection */
>         tvout_vip_set_sel_input(tvout, TVO_VIP_DVO, main_path,
> -                               sel_input_logic_inverted,
>                                 STI_TVOUT_VIDEO_OUT_RGB);
>  }
>
> @@ -357,8 +347,6 @@ static void tvout_dvo_start(struct sti_tvout *tvout, bool main_path)
>   */
>  static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
>  {
> -       struct device_node *node = tvout->dev->of_node;
> -       bool sel_input_logic_inverted = false;
>         u32 tvo_in_vid_format;
>
>         dev_dbg(tvout->dev, "%s\n", __func__);
> @@ -391,16 +379,12 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
>         /* set round mode (rounded to 8-bit per component) */
>         tvout_vip_set_rnd(tvout, TVO_VIP_HDMI, TVO_VIP_RND_8BIT_ROUNDED);
>
> -       if (of_device_is_compatible(node, "st,stih407-tvout")) {
> -               /* set input video format */
> -               tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format,
> -                                       TVO_IN_FMT_SIGNED);
> -               sel_input_logic_inverted = true;
> -       }
> +       /* set input video format */
> +       tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
>
>         /* input selection */
>         tvout_vip_set_sel_input(tvout, TVO_VIP_HDMI, main_path,
> -                       sel_input_logic_inverted, STI_TVOUT_VIDEO_OUT_RGB);
> +                               STI_TVOUT_VIDEO_OUT_RGB);
>  }
>
>  /**
> @@ -412,8 +396,6 @@ static void tvout_hdmi_start(struct sti_tvout *tvout, bool main_path)
>   */
>  static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
>  {
> -       struct device_node *node = tvout->dev->of_node;
> -       bool sel_input_logic_inverted = false;
>         u32 tvo_in_vid_format;
>         int val;
>
> @@ -449,16 +431,11 @@ static void tvout_hda_start(struct sti_tvout *tvout, bool main_path)
>         /* set round mode (rounded to 10-bit per component) */
>         tvout_vip_set_rnd(tvout, TVO_VIP_HDF, TVO_VIP_RND_10BIT_ROUNDED);
>
> -       if (of_device_is_compatible(node, "st,stih407-tvout")) {
> -               /* set input video format */
> -               tvout_vip_set_in_vid_fmt(tvout,
> -                       tvo_in_vid_format, TVO_IN_FMT_SIGNED);
> -               sel_input_logic_inverted = true;
> -       }
> +       /* Set input video format */
> +       tvout_vip_set_in_vid_fmt(tvout, tvo_in_vid_format, TVO_IN_FMT_SIGNED);
>
>         /* Input selection */
>         tvout_vip_set_sel_input(tvout, TVO_VIP_HDF, main_path,
> -                               sel_input_logic_inverted,
>                                 STI_TVOUT_VIDEO_OUT_YUV);
>
>         /* power up HD DAC */
> @@ -906,7 +883,6 @@ static int sti_tvout_remove(struct platform_device *pdev)
>  }
>
>  static const struct of_device_id tvout_of_match[] = {
> -       { .compatible = "st,stih416-tvout", },
>         { .compatible = "st,stih407-tvout", },
>         { /* end node */ }
>  };
> --
> 1.9.1
>



-- 
Benjamin Gaignard

Graphic Study Group

Linaro.org │ Open source software for ARM SoCs

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