drm: fourcc byteorder: add bigendian support to drm_mode_legacy_fb_format

[Jochen Rollwagen]

Hello there,

Since I’m on a big-endian system I’ve been following the discusssion and 
have two (maybe not quite related, and possibly dumb) questions:

1.There’s been a similar discussion on mesa-dev concerning big-endian 
and #ifdef’s, see

https://lists.freedesktop.org/archives/mesa-dev/2016-February/107701.html

Without checking whether the #defines are actually, well, #defined it’s 
doubtful whether the patch would have any effect on all platforms. 
conclusion from the discussion above was that the whole big-endian 
#ifdef story is „/a very fragile situation/„

2. I’ve recently stumbled across a register definition for (older) 
radeon GPU’s, what caught my eye was

*CB:RB3D_COLORPITCH[0-3] · [R/W] · 32 bits · Access: 8/16/32 · 
MMReg:0x4e38-0x4e44 *

*DESCRIPTION: */Color buffer format and tiling control for all the 
multibuffers and the pitch of multibuffer 0. Unpipelined. The cache must 
be empty before any of the registers are changed. /

Field Name

	

Bits

	

Default

	

Description

COLORPITCH

	

13:1

	

none

	

3D destination pitch in multiples of 2-pixels.

COLORTILE

	

16

	

none

	

Denotes whether the 3D destination is in macrotiled format. POSSIBLE 
VALUES: 00 - 3D destination is not macrotiled 01 - 3D destination is 
macrotiled

COLORMICROTILE

	

18:17

	

none

	

Denotes whether the 3D destination is in microtiled format. POSSIBLE 
VALUES: 00 - 3D destination is no microtiled 01 - 3D destination is 
microtiled 02 - 3D destination is square microtiled. Only available in 
16-bit 03 - (reserved)

COLORENDIAN

	

20:19

	

none

	

Specifies endian control for the color buffer

POSSIBLE VALUES: 00 - No swap 01 - Word swap (2 bytes in 16-bit) 02 - 
Dword swap (4 bytes in a 32-bit) 03 - Half-Dword swap (2 16-bit in a 
32-bit)

COLORFORMAT

	

24:21

	

0x6

	

3D destination color format. POSSIBLE VALUES: 00 - (Reserved) 01 - 
(Reserved) 02 - (Reserved) 03 - ARGB1555 04 - RGB565 05 - (Reserved) 06 
- ARGB8888 07 - ARGB32323232 08 - (Reserved) 09 - I8 10 - ARGB16161616 
11 - YUV422 packed (VYUY) 12 - YUV422 packed (YVYU) 13 - UV88 14 - 
(reserved) 15 - ARGB4444

Dumb question: Could that register be used for just setting the GPU to 
big-endian mode and leave all the swapping to the GPU ?

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