[radeon-alex:drm-next-4.16-wip 105/117] drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:119:21: sparse: cast removes address space of expression

[kbuild test robot]

tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next-4.16-wip
head:   8f003334f9f06d5a4c03c3d966ba258d770b97f4
commit: b8e7f06f8cc17c9f978987c9b98886f6e338a506 [105/117] drm/amdgpu: move debugfs functions to their own file
reproduce:
        # apt-get install sparse
        git checkout b8e7f06f8cc17c9f978987c9b98886f6e338a506
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)


vim +119 drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c

    66	
    67	static ssize_t amdgpu_debugfs_regs_read(struct file *f, char __user *buf,
    68						size_t size, loff_t *pos)
    69	{
    70		struct amdgpu_device *adev = file_inode(f)->i_private;
    71		ssize_t result = 0;
    72		int r;
    73		bool pm_pg_lock, use_bank;
    74		unsigned instance_bank, sh_bank, se_bank;
    75	
    76		if (size & 0x3 || *pos & 0x3)
    77			return -EINVAL;
    78	
    79		/* are we reading registers for which a PG lock is necessary? */
    80		pm_pg_lock = (*pos >> 23) & 1;
    81	
    82		if (*pos & (1ULL << 62)) {
    83			se_bank = (*pos & GENMASK_ULL(33, 24)) >> 24;
    84			sh_bank = (*pos & GENMASK_ULL(43, 34)) >> 34;
    85			instance_bank = (*pos & GENMASK_ULL(53, 44)) >> 44;
    86	
    87			if (se_bank == 0x3FF)
    88				se_bank = 0xFFFFFFFF;
    89			if (sh_bank == 0x3FF)
    90				sh_bank = 0xFFFFFFFF;
    91			if (instance_bank == 0x3FF)
    92				instance_bank = 0xFFFFFFFF;
    93			use_bank = 1;
    94		} else {
    95			use_bank = 0;
    96		}
    97	
    98		*pos &= (1UL << 22) - 1;
    99	
   100		if (use_bank) {
   101			if ((sh_bank != 0xFFFFFFFF && sh_bank >= adev->gfx.config.max_sh_per_se) ||
   102			    (se_bank != 0xFFFFFFFF && se_bank >= adev->gfx.config.max_shader_engines))
   103				return -EINVAL;
   104			mutex_lock(&adev->grbm_idx_mutex);
   105			amdgpu_gfx_select_se_sh(adev, se_bank,
   106						sh_bank, instance_bank);
   107		}
   108	
   109		if (pm_pg_lock)
   110			mutex_lock(&adev->pm.mutex);
   111	
   112		while (size) {
   113			uint32_t value;
   114	
   115			if (*pos > adev->rmmio_size)
   116				goto end;
   117	
   118			value = RREG32(*pos >> 2);
 > 119			r = put_user(value, (uint32_t *)buf);
   120			if (r) {
   121				result = r;
   122				goto end;
   123			}
   124	
   125			result += 4;
   126			buf += 4;
   127			*pos += 4;
   128			size -= 4;
   129		}
   130	
   131	end:
   132		if (use_bank) {
   133			amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
   134			mutex_unlock(&adev->grbm_idx_mutex);
   135		}
   136	
   137		if (pm_pg_lock)
   138			mutex_unlock(&adev->pm.mutex);
   139	
   140		return result;
   141	}
   142	

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