[PATCH v3 2/2] drm: rcar-du: calculate DPLLCR to be more small jitter
kuninori.morimoto.gx at renesas.com
Sun Dec 17 23:46:29 UTC 2017
> >> > From: Kuninori Morimoto <kuninori.morimoto.gx at renesas.com>
> >> > In general, PLL has VCO (= Voltage controlled oscillator),
> >> > one of the very important electronic feature called as "jitter"
> >> > is related to this VCO.
> >> > In academic generalism, VCO should be maximum to be more small jitter.
> >> > In high frequency clock, jitter will be large impact.
> >> > Thus, selecting Hi VCO is general theory.
> >> Thanks for your patch!
> >> > One note here is that it should be 2000 < fvco < 4096MHz
> >> 2000 Hz? (else it could be misinterpreted that MHz applies to both values).
> > Laurent had asked same question ;)
> > But, yes, it is 2000 Hz
> I've seen his question, that's why I think you should make it unambiguous.
Ahh... OK yes indeed
will fix in v4
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